Row decoder and non-volatile memory device

A row decoder comprising:

• a first driver including a first input terminal configured to receive a first voltage, the first driver configured to generate a first control signal for controlling a first cell transistor of a memory cell;
• and
• a second driver including a second input terminal and a third input terminal configured to receive a second voltage and a third voltage, respectively, the second driver configured to generate a second control signal for controlling a second cell transistor of the memory cell,
• wherein the first driver comprises:
• a first NMOS transistor formed on a first P-well that is formed on a first N-well;
• and
• a first PMOS transistor formed on a second N-well disposed adjacent to the first N-well,
• wherein the second driver comprises:
• a second PMOS transistor formed on a third N-well separated from the first N-well;
• and
• a second NMOS transistor formed on a second P-well that is formed on the third N-well.

A semiconductor memory device comprising:

• a plurality of memory cells;
• and
• a row decoder comprising a first driver and second driver;
• wherein the first driver includes a first PMOS transistor and a first NMOS transistor disposed adjacent to the first PMOS transistor, the first NMOS transistor is formed on a first N-well,
• wherein the second driver includes a second PMOS transistor and a second NMOS transistor disposed adjacent to the second PMOS transistor, the second NMOS transistor is formed on a second N-well different from the first N-well, and
• wherein the first NMOS transistor and second NMOS transistor are adjacent transistor and are disposed between the first PMOS transistor and second PMOS transistor.