Fusion memory

A semiconductor memory, comprising:

• a semiconductor substrate;
• and
• a first memory cell array formed on the semiconductor substrate by arranging a plurality of first NAND cell units,
• the first NAND cell unit of the first memory cell array comprising a non-volatile memory cell including a first transistor and a first and a second selective transistor each including a second transistor, the first transistor having a stacked structure in which a first insulation film, a first gate film, a second insulation film, and a second gate film are stacked on the substrate, and having a two-layer gate structure in which a source region and a drain region are formed on both sides interposing a channel region below the first insulation film, the second transistor having a structure same as the structure of the first transistor except for having a two-layer gate structure in which an opening is provided in the second insulation film and the first gate film and the second gate film are electrically connected,
• the non-volatile memory cells being connected in series in a source/drain direction and the first and second selective transistors are connected to first and second ends respectively of a serial connection portion connecting the non-volatile memory cells in series, wherein
• a second memory cell array formed by arranging a plurality of second NAND cell units on the semiconductor substrate,
• the second NAND cell unit of the second memory cell array comprising a plurality of third transistors on the substrate and a fourth and fifth transistor at first and second ends respectively of a serial connection portion connecting the third transistors in serial, the third transistor having a structure same as the structure of the first transistor, the fourth transistor having a structure same as the structure of the second transistor, wherein
• the first memory cell array functions as a non-volatile memory configured to store information depending on variation in threshold voltage by variation in amount of electrons injected and released into and from the first gate film, and
• the second memory cell array functions as a volatile memory configured to store information depending on variation in potential by variation in charge stored in an inner channel node of the second NAND cell unit.

A semiconductor memory, comprising:

• a first memory cell array configured to store information by injecting an electron into a floating gate;
• and
• a second memory cell array configured to store information by storing an electron in a capacitor, the second memory cell array being formed on the same semiconductor substrate as the first memory cell array, wherein
• a first bit line of the first memory cell array is connected to a first latch circuit configured to read data from the first bit line and store information used to write data via the first bit line, and a second bit line of the second memory cell array is connected to a second latch circuit configured to read data via the second bit line and store information used to write data via the second bit line, the semiconductor memory further comprising:
• a logic operation circuit for every second latch circuit, the logic operation circuit implementing a logic operation using information of the second latch circuit and information of the first latch circuit as an input;
• and
• a controller configured to return a result of the logic operation of the logic operation circuit to one of the second latch circuit or the first latch circuit.