Sub-threshold memory cell circuit with high density and high robustness

A high-density and high-robustness sub-threshold memory cell circuit, which is provide with high-density and high-robustness sub-threshold memory cell circuit with double-end writing and single-end reading features, comprising two PMOS transistors P1 and P2 and five NMOS transistors N1, N2, N3, N4, and N5, all of said seven transistors form the said sub-threshold memory cell circuit;

• wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4 and N5 is connected with the local grid electrode respectively, the base electrode and source electrode of the NMOS transistors N1 and N2 are grounded respectively, the source electrode of the two PMOS transistors are connected with the supply voltage, the drain electrode and grid electrode of the NMOS transistor N1 are connected with the drain electrode and grid electrode of the PMOS transistor P1, respectively, so as to form a phase inverter;
• the drain electrode and grid electrode of the NMOS transistor N2 are connected with the drain electrode and grid electrode of the PMOS transistor P2 respectively so as to form another phase inverter;
• the drain electrode of the NMOS transistor N1 and the drain electrode of the PMOS transistor P1 are connected with the grid electrode of the NMOS transistor N2 and the grid electrode of the PMOS transistor P2 respectively, the connection end between the grid electrode of the NMOS transistor N1 and the grid electrode of the PMOS transistor P1 and the connection end between the drain electrode of the NMOS transistor N2 and the drain electrode of the PMOS transistor P2 are connected with either the source electrode or drain electrode of the NMOS transistor N5 respectively, the grid electrode of the NMOS transistor N5 is connected with the NOT read word line (NOT RWL) of external control signal, the connection end between the drain electrode of the NMOS transistor N1 and the drain electrode of the PMOS transistor P1 and the write bit line are connected with either the source electrode or drain electrode of the NMOS transistor N3 respectively, the grid electrode of the NMOS transistor N3 is connected with the write word line (WWL), the connection end between the drain electrode of the NMOS transistor N2 and the drain electrode of the PMOS transistor P2 and the bit line shared by the NOT write bit line (NOT WBL) and the read bit line (RBL) are connected with either the source electrode or drain electrode of the NMOS transistor N4 respectively, the grid electrode of the NMOS transistor N4 is connected with the word line shared by the write word line (WWL) and the read word line (RWL).