US 8,559,212 B2Granted

Memory circuit and word line control circuit

AssigneeMediatek Inc.

InventorShih-Huang Huang

Life of this patent

Estimating the term…

Loading patent…

Abstract

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

Claims15

Dependent claims

A memory circuit, comprising:

a first PMOS transistor, coupled between a first voltage terminal and a first node;
a second PMOS transistor, coupled between the first voltage terminal and a second node;
a first NMOS transistor, coupled between a third node and a second voltage terminal;
a second NMOS transistor, coupled between a fourth node and the second voltage terminal;
a memory cell array, comprising a plurality of memory cells, wherein at least one of the memory cells comprises a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node;
a control circuit capable of controlling gate voltages of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor, and when the memory circuit operates in a power down mode, the control circuit is capable of controlling the gate voltages to turn on the first PMOS transistor, turn off the second PMOS transistor, turn off the first NMOS transistor, and turn on the second NMOS transistor, to pull an output voltage of the first inverter of the memory cell to a logic high voltage and pull an output voltage of the second inverter of the memory cell to a logic low voltage.

3 more elements

A memory circuit, comprising:

a first PMOS transistor, coupled between a fifth node and a first node;
a second PMOS transistor, coupled between the fifth node and a second node;
a third PMOS transistor, coupled between a first voltage terminal and the fifth node, having a gate coupled to the fifth node;
a fourth PMOS transistor, coupled between the first voltage terminal and the fifth node;
a first NMOS transistor, coupled between a third node and a sixth node;
a second NMOS transistor, coupled between a fourth node and the sixth node;
a third NMOS transistor, coupled between the sixth node and a second voltage terminal, having a gate coupled to the sixth node;
a fourth NMOS transistor, coupled between the sixth node and the second voltage terminal;
and
a memory cell array, comprising a plurality of memory cells, wherein at least one of the memory cells comprises a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

7 more elements

A memory circuit, comprising:

a first PMOS transistor, coupled between a first voltage terminal and a first node;
a second PMOS transistor, coupled between the first voltage terminal and a second node;
a third PMOS transistor, coupled between the first voltage terminal and a fifth node;
a fourth PMOS transistor, coupled between the first node and the fifth node, having a gate coupled to the first node;
a fifth PMOS transistor, coupled between the second node and the fifth node, having a gate coupled to the second node;
a first NMOS transistor, coupled between a third node and a second voltage terminal;
a second NMOS transistor, coupled between a fourth node and the second voltage terminal;
a third NMOS transistor, coupled between a sixth node and the second voltage terminal;
a fourth NMOS transistor, coupled between the sixth node and the third node, having a gate coupled to the third node;
a fifth NMOS transistor, coupled between the sixth node and the fourth node, having a gate coupled to the fourth node;
and
a memory cell array, comprising a plurality of memory cells, wherein at least one of the memory cells comprises a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/176,852Filed 6 Jul 2011
Published: US 2013/0010531 A110 Jan 2013
Granted: 15 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 5/148
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: details…
G11C 7/20
Arrangements for writing information into, or reading information out from, a digital store: memory cell initialisation circuits, e.g. when…
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…