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US 8,559,211 B2Granted
Phase change memory device
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
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Abstract
A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
Claims8
A memory device, comprising:
- a semiconductor substrate;
- a plurality of cell arrays stacked above the semiconductor substrate, each of the plurality of cell arrays having a plurality of memory cells, bit lines coupled to first ends of the memory cells and word lines coupled second ends of the memory cells, each of the plurality of memory cells including a variable resistance element to be set at a resistance value and an access element connected in series to the variable resistance element;
- and
- a booster circuit formed on the semiconductor substrate for generating a boosted write pulse with a charge-pump operation and for providing the boosted write pulse to a selected bit line or a selected word line.
1 more element
Dependencies are inferred from the claim text.