Ferroelectric random access memory and memory system
AssigneeKabushiki Kaisha Toshiba
InventorRyousuke Takizawa
Life of this patent
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Abstract
In one embodiment, a non-volatile memory includes a first buffer that receives notification of power-down and outputs a first signal changed from a first value to a second value based on the notification, a first controlling unit that receives and outputs a command signal, a second controlling unit that generates and outputs a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value, a memory cell array in which memory cells are arrayed, and a sense amplifier circuit that reads data from the memory cell.
Claims20
A non-volatile memory comprising:
- a first buffer configured to receive a notification of a power-down and output a first signal changed from a first value to a second value based on the notification;
- a first controlling unit configured to receive and output a command signal;
- a second controlling unit configured to generate and output a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value;
- a memory cell array comprising memory cells;
- and
- a sense amplifier circuit configured to read data from the memory cell.
A non-volatile memory comprising:
- a first buffer configured to receive a notification of a power-down and output a first signal changed from a first value to a second value based on the notification;
- a first controlling unit configured to receive and output a command signal and generate and output a second signal that is changed from a third value to a fourth value with the reception of a write command and is changed from the fourth value to the third value after an elapse of a first time from the reception of write data;
- a delaying unit configured to generate and output a third signal that is changed from a fifth value to a sixth value with the change of the first signal from the second value to the first value and is changed from the sixth value to the fifth value when the first signal is changed from the first value to the second value and the second signal has the third value;
- a second controlling unit configured to generate and output a basic signal that has a seventh value when the command signal output from the first controlling unit indicates an active command, and has an eighth value when the command signal indicates a command corresponding to a write back instruction or the third signal has the fifth value;
- a memory cell array comprising memory cells;
- and
- a sense amplifier circuit configured to read data from the memory cell.
A memory system comprising:
- a non-volatile memory comprising a first buffer, a first controlling unit, a second controlling unit, a memory cell array comprising memory cells, and a sense amplifier circuit configured to read data from the memory cell array;
- and
- a memory controller configured to output a first command signal corresponding to a read instruction and a second command signal corresponding to a write back instruction to the first controlling unit, and notify power-down to the first buffer when a source voltage is detected and the source voltage is less than a first value,
- wherein the first buffer is configured to output a first signal changed from a first value to a second value based on the notification, and
- the second controlling unit is configured to generate and output a basic signal that has a third value when the first controlling unit receives the first command signal and has a fourth value when the first controlling unit receives the second command signal or the first signal has the second value.
Dependencies are inferred from the claim text.