Integrated circuit package system with stackable devices and a method of manufacture thereof
AssigneeSTATS ChipPAC, Ltd.
InventorsSang-Ho Lee, Soo-San Park, DaeSik Choi
Life of this patent
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Abstract
An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
Claims20
A method for manufacturing an integrated circuit package system comprising:
- providing a package substrate;
- mounting an interposer chip containing active circuitry over the package substrate;
- attaching a conductive bump stack, including at least two conductive bond bumps, having a base bump end and a stud bump end, the base bump end on the interposer chip;
- connecting a stack connector to the interposer chip and the package substrate;
- and
- applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
A method for manufacturing an integrated circuit package system comprising:
- providing a package substrate having a component side;
- mounting an interposer chip containing active circuitry and having a chip bond pad adjacent an active chip surface over the package substrate;
- attaching a conductive bump stack, including at least two conductive bond bumps, having a base bump end and a stud bump end, the base bump end on the interposer chip;
- connecting a stack connector to the interposer chip and the component side of the package substrate;
- and
- applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack providing the stud bump end substantially exposed adjacent the package encapsulant.
An integrated circuit package system comprising:
- a package substrate;
- an interposer chip containing active circuitry mounted over the package substrate;
- a conductive bump stack, including at least two conductive bond bumps, having a base bump end and a stud bump end, the base bump end on the interposer chip;
- a stack connector connected to the interposer chip and the package substrate;
- and
- a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
Dependencies are inferred from the claim text.