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US 8,559,154 B2Granted
Systems and methods for switching a relay at zero cross
AssigneeOsram Sylvania Inc.
InventorsWei Li, Canyon Bliss
Life of this patent
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Abstract
Circuitry, systems and methods that address the need to coordinate relay switching with another event, such as a zero crossing of an alternating current (AC) voltage waveform are described. In some embodiments, the systems and methods continuously or periodically calibrate the timing of control signals to a relay, such that the switching of the relay in response to some (e.g., second or subsequent) control signals occurs closer in time to a zero crossing of an AC line voltage than the switching of the relay in response to other (e.g., initial or first) control signals.
Claims18
A system, comprising:
- a line status circuit configured to receive a line voltage and output a line status output representative of a first zero crossing ZC1 of the line voltage;
- a processor circuit configured to output at least one first relay control signal in response to a line status output;
- a relay coupled to first, second and third line voltage inputs and configured to switch in response to the at least one first relay control signal, thereby coupling or decoupling the second and third line voltage inputs relative to a second zero crossing ZC2 of the line voltage;
- a relay status circuit configured to output a relay status output representative of a first switching of the relay in response to the at least one first relay control signal;
- and
- wherein the processor circuit is further configured to output at least one subsequent relay control signal, so as to trigger a subsequent switching of the relay, relative to at least one subsequent zero crossing ZCn of the line voltage, and wherein the subsequent switching occurs closer in time to the at least one zero crossing ZCn than the first switching occurs relative to the second zero crossing ZC2.
3 more elements
A method, comprising:
- outputting a line status output representative of a first zero crossing ZC1 of a line voltage from a line status circuit;
- outputting at least one first relay control signal from a processor circuit in response to the line status output after a known delay time D3, relative to the first zero crossing ZC1;
- first switching a relay in response to the first relay control signal, so as to couple and decouple second and third line voltage inputs with the relay, the relay further coupled to a first line voltage input, the first switching occurring relative to a second zero crossing ZC2 of the line voltage;
- outputting a relay status output representative of the first switching;
- calculating an error D4 with the processor circuit, wherein the error D4 correlates to the time elapsing between a moment t1 of the second zero crossing ZC2 and a moment t2 wherein the processor circuit receives the relay status output;
- and
- outputting at least one subsequent relay control signal from the processor circuit, so as to trigger a subsequent switching of the relay, relative to at least one subsequent zero crossing ZCn of the line voltage;
- wherein the subsequent switching occurs closer in time to the at least one subsequent zero crossing ZCn than the first switching occurs relative to the second zero crossing ZC2.
5 more elements
An article comprising a tangible storage medium having calibration instructions stored thereon, which when executed by a processor result in operations comprising:
- outputting a line status output representative of a first zero crossing ZC1 of a line voltage from a line status circuit;
- outputting at least one first relay control signal from a processor circuit in response to the line status output after a known delay time D3, relative to the first zero crossing ZC1;
- first switching a relay in response to the first relay control signal, so as to couple and decouple second and third line voltage inputs with the relay, the relay further coupled to a first line voltage input, the first switching occurring relative to a second zero crossing ZC2 of the line voltage;
- outputting a relay status output representative of the first switching;
- calculating an error D4 with the processor circuit, the error D4 correlating to the time elapsing between a moment t1 of the second zero crossing ZC2 and a moment t2 wherein the processor circuit receives the relay status output;
- and
- outputting at least one subsequent relay control signal from the processor circuit signal so as to trigger a subsequent switching of the relay, relative to at least one subsequent zero crossing ZCn of the line voltage;
- wherein the subsequent switching occurs closer in time to the at least one subsequent zero crossing ZCn than the first switching occurs relative to the second zero crossing ZC2.
5 more elements
Dependencies are inferred from the claim text.