Solid state imaging device and camera system
AssigneeSony Corporation
InventorsTetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
Life of this patent
Estimating the term…
Abstract
A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example −1V).
Claims5
A solid state imaging device comprising:
- a plurality of unit pixels formed in an imaging area, each unit pixel having (a) a photoelectric converter for generating a charge in accordance with an amount of incident light, (b) a floating node for storing the charge from the photoelectric converter, and (c) a reset transistor for resetting the floating node;
- and
- a plurality of potentials supplied to a gate electrode of the reset transistor when bringing the reset transistor from an ON state to an OFF state to set the gate of the reset transistor to a negative potential after passing a ground level potential from a positive high level potential.
A solid state imaging device comprising:
- a plurality of unit pixels formed in an imaging area, each unit pixel having (a) a photoelectric converter for generating a charge in accordance with an amount of incident light, (b) a floating node for storing the charge from the photoelectric converter, and (c) a reset transistor for resetting the floating node;
- circuitry supplying at least three or more potentials which are supplied to a gate electrode of the reset transistor, at least one of the potentials being a negative potential;
- and
- a portion of the device which is able to set the gate potential of the reset transistor, when bringing the reset transistor from an ON state to an OFF state, to the negative potential after passing a ground level potential from a positive high level potential.
Dependencies are inferred from the claim text.