Robust gain and phase calibration method for a time-interleaved analog-to-digital converter
AssigneeIntersil Americas Inc.
InventorSunder S. Kidambi
Life of this patent
Estimating the term…
Abstract
A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.
Claims25
An analog to digital converter (ADC) apparatus comprising:
- a clock signal generator, for generating a clock signal;
- a first ADC coupled to the clock signal generator, the first ADC converting an input signal to provide a first digital signal;
- a second ADC coupled to the clock signal generator, the second ADC converting the input signal to provide a second digital signal;
- wherein the input signal has an unused spectral portion that lies within a Nyquist zone of the first and second ADCs;
- a first digital filter, for filtering the first digital signal, to provide a first filtered signal, with the first digital filter having a frequency response that attenuates components of the first digital signal that aliased as a result of the first ADC;
- a second digital filter, for filtering the second digital signal, to provide a second filtered signal, the second digital filter having a frequency response that attenuates components of the second digital signal that are aliased as a result of the second ADC;
- an error measurement block coupled to receive the first and second filtered signals, the error measurement block producing an error measurement signal based on the first and second filtered signals;
- an adaptive processor coupled to receive the error signal, the adaptive processor estimating at least one of offset, gain, and sample-time error between the first and second ADCs based on the error measurement signal, the adaptive processor feeding back a correction signal corresponding to the estimated error to correct one of offset, gain, and sample-time error of at least one of the first and second ADCs;
- and
- a multiplexer, for interleaving the first and second digital signals to form a digital representation of the input signal.
A method comprising:
- converting an input signal with two Analog to Digital Converters (ADC) cores, to provide to a set of two ADC outputs as two digital signals, the input signal having an unused spectral portion that lies within a Nyquist zone of the first and second ADCs;
- and
- at least one of the ADC cores having at least one of an offset correction, a gain correction, or a sample time correction;
- interleaving the two digital signals output by the ADC cores to form a digital representation of the input signal;
- filtering the two digital signals to produce corresponding two filtered signals, a frequency response of the filtering depending upon an expected aliasing characteristic of the input signal;
- estimating at least one of gain or sample time error from at least one of the filtered signals;
- and
- determining a corresponding one of the gain correction or phase correction, from the gain or sample time error, applied to at least one of the ADC cores.
A tangible, non-transitory, computer readable medium for storing computer executable instructions for converting an input signal, with the computer executable instructions for:
- receiving two digital signals from a corresponding number of Analog to Digital Converters (ADC) cores, the input signal having an unused spectral portion that lies within a Nyquist zone of the first and second ADCs;
- and
- at least some of the ADC cores having at least one of an offset correction input, a gain correction input, or a phase correction input;
- filtering one or more of the two digital signals to produce corresponding one or more filtered signals, with a frequency response of the filtering depending upon an expected aliasing characteristic of the input signal;
- estimating at least one of gain or sample time error from the one or more filtered signals;
- and
- determining a corresponding one of the gain correction input or phase correction input, from the gain or sample time error, applied to at least one of the ADC cores.
Dependencies are inferred from the claim text.