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US 8,558,607 B2Granted
Charge-domain filter and method thereof
AssigneeIndustrial Technology Research Institute
InventorMing-Feng Huang
Life of this patent
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Abstract
A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.
Claims27
A charge-domain filter, comprising:
- a switched-capacitor network, having an input terminal receiving an input signal, and the switched-capacitor network sampling the input signal according to a plurality of clock signals, wherein the clock signals have different phases;
- and
- a clock generator, coupled to the switched-capacitor network for providing the clock signals, wherein the clock generator adjusts phase differences of the clock signals according to a first control signal or adjusts pulse widths of the clock signals according to a second control signal, and the clock generator comprises:
- N unit pulse cells UPC_1-UPC_N, connected in series, wherein an ith unit pulse cell UPC_i samples an (i−1)th delay clock output by an (i−1)th unit pulse cell UPC_(i−1) according to a first frequency, so as to obtain an ith pulse signal, the ith unit pulse cell UPC_i delays the ith pulse signal according to the first control signal to obtain an ith delay clock, and the ith unit pulse cell UPC_i outputs the ith delay clock to an (i+1)th unit pulse cell UPC_(i+1);
- and
- N programmable width cells PWC_1-PWC_N, wherein an ith programmable width cell PWC_i is coupled to the ith unit pulse cell UPC_i for receiving the ith pulse signal, the ith programmable width cell PWC_i adjusts a pulse width of the ith pulse signal according to the second control signal, so as to obtain an ith clock signal clki of the clock signals, and the ith programmable width cell PWC_i outputs the ith clock signal clki to the switched-capacitor network.
3 more elements
A clock generator, adapted to generate a plurality of clock signals, and the clock generator comprising:
- N unit pulse cells UPC_1-UPC_N, connected in series, wherein an ith unit pulse cell UPC_i samples an (i−1)th delay clock output by an (i−1)th unit pulse cell UPC_(i−1) according to a first frequency, so as to obtain an ith pulse signal, the ith unit pulse cell UPC_i delays the ith pulse signal according to a first control signal to obtain an ith delay clock, and the ith unit pulse cell UPC_i outputs the ith delay clock to an (i+1)th unit pulse cell UPC_(i+1);
- and
- N programmable width cells PWC_1-PWC_N, wherein an ith programmable width cell PWC_i is coupled to the ith unit pulse cell UPC_i for receiving the ith pulse signal, and the ith programmable width cell PWC_i adjusts a pulse width of the ith pulse signal according to a second control signal, so as to obtain an ith clock signal clki of the clock signals.
A charge-domain filtering method, comprising:
- receiving an input signal by a switched-capacitor network, and sampling the input signal according to a plurality of clock signals, wherein the clock signals have different phases;
- and
- adjusting phase differences and pulse widths of the clock signals generated by a clock generator according to at least one control signal, wherein the clock generator comprises:
- N unit pulse cells UPC_1-UPC_N, connected in series, wherein an ith unit pulse cell UPC_i samples an (i−1)th delay clock output by an (i−1)th unit pulse cell UPC_(i−1) according to a first frequency, so as to obtain an ith pulse signal, the ith unit pulse cell UPC_i delays the ith pulse signal according to the first control signal to obtain an ith delay clock, and the ith unit pulse cell UPC_i outputs the ith delay clock to an (i+1)th unit pulse cell UPC_(i+1);
- and
- N programmable width cells PWC_1-PWC_N, wherein an ith programmable width cell PWC_i is coupled to the ith unit pulse cell UPC_i for receiving the ith pulse signal, the ith programmable width cell PWC_i adjusts a pulse width of the ith pulse signal according to the second control signal, so as to obtain an ith clock signal clki of the clock signals, and the ith programmable width cell PWC_i outputs the ith clock signal clki to the switched-capacitor network.
3 more elements
Dependencies are inferred from the claim text.