US 8,558,602 B2Granted

Semiconductor integrated circuit

AssigneeKabushiki Kaisha Toshiba

InventorsRyo Fukuda, Masaru Koyanagi

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Abstract

According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

Claims19

Dependent claims

A semiconductor integrated circuit comprising:

a first level shifter that includes:
a first transistor of a first channel type having a source terminal connected to a power source voltage supply node of a first power source system,
a second transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system, a drain terminal connected to a gate terminal of the first transistor and a gate terminal connected to a drain terminal of the first transistor,
a third transistor of a second channel type having a drain terminal connected to the drain terminal of the first transistor, a source terminal connected to a ground voltage supply node and a gate terminal to which a first signal of a second power source system is input, and
a fourth transistor of the second channel type having a drain terminal connected to the drain terminal of the second transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which an inversion signal of the first signal is input, and
a second level shifter that includes:
a fifth transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system,
a sixth transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system, a drain terminal connected to a gate terminal of the fifth transistor and a gate terminal connected to a drain terminal of the fifth transistor,
a seventh transistor of a second channel type having a drain terminal connected to the drain terminal of the fifth transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which a second signal of the second power source system is input, and
an eighth transistor of the second channel type having a drain terminal connected to the drain terminal of the sixth transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which a signal of a common drain terminal of the drain terminal of the second transistor and the drain terminal of the fourth transistor is input.

7 more elements

A semiconductor integrated circuit comprising:

a first level shifter configured to shift a level of a first signal from a first power source system to a second power source system, and to output a signal;
a second level shifter configured to shift an inversion signal of the first signal from the first power source system to the second power source system by the signal output from the first level shifter;
the first level shifter comprising first transistors of a first channel type and second transistors of a second channel type, the first transistors having sources to which the second power source system is supplied, and having drains and gates which are cross-coupled, and the second transistors having drains which are coupled to drains of the first transistors, and having gates which are controlled by the first signal and the inversion signal, wherein the signal output from the first level shifter is derived from a node coupled to said drains;
and
the second level shifter comprising third transistors of the first channel type and fourth transistors of the second channel type, the third transistors having sources to which the second power source system is supplied, and having drains and gates which are cross-coupled, said fourth transistors having drains which are coupled to drains of the third transistors, and having gates which are controlled by the inversion signal and the signal output from the first level shifter.

2 more elements

Dependencies are inferred from the claim text.