US 8,558,601 B2Granted

Gate driving circuit

AssigneeLG Display Co., Ltd.

InventorsYong-Ho Jang, Seung-Chan Choi, Jae-Yong You, Woo-Seok Choi

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Abstract

Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse.

Claims20

Dependent claims

A gate driving circuit comprising:

a first clock generator to sequentially output n (n being a natural number equal to or greater than 2) output clock pulses having different phases in a circulating manner;
a second clock generator to sequentially output n output control clock pulses having different phases in a circulating manner;
and
a shift register to receive the n output clock pulses from the first clock generator and the n output control clock pulses from the second clock generator and to sequentially output a plurality of scan pulses, wherein
high sections of k-th to (k+s)-th (s being a natural number greater than 1) output clock pulses output during adjacent periods overlap with one another for a predetermined time,
a k-th output control clock pulse rises before the k-th output clock pulse,
the k-th output control clock pulse falls before a (k−a)-th (a being a natural number less than k) output clock pulse,
a high section of at least one of the output control clock pulses does not overlap with that of the k-th output clock pulse, and
a (k+b)-th (b being a natural number) output clock pulse falls during the high section of the at least one of the output control clock pulses not overlapping with that of the k-th output clock pulse.

6 more elements

Dependencies are inferred from the claim text.