Back to results
US 8,558,599 B1Granted
Method and apparatus for reducing power spikes caused by clock networks
AssigneeAltera Corporation
InventorsDavid Lewis, Ryan Fung
Life of this patent
Estimating the term…
Abstract
A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.
Claims19
A clock network, comprising:
- a first plurality of shield wires associated with a first plurality of clock lines connected to a clock signal, wherein the first plurality of clock lines is shielded by only the first plurality of shield wires;
- a second plurality of shield wires associated with a second plurality of clock lines connected to the clock signal, wherein the second plurality of clock lines are shielded by only the second plurality of shield wires;
- a first plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the first plurality of clock activity program circuits is coupled to one clock line of the first plurality of clock lines, and wherein the first plurality of clock activity program circuits delivers an active high clock signal on the first plurality of clock lines to a first plurality of components;
- and
- a second plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the second plurality of clock activity program circuits is coupled to one clock line of the second plurality of clock lines, wherein the second plurality of clock activity program circuits delivers an active low clock signal on the second plurality of clock lines to a second plurality of components, and wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes generated by the clock network.
2 more elements
A clock network, comprising:
- a first plurality of shield wires associated with a first plurality of clock lines connected to a clock signal, wherein the first plurality of clock lines is shielded by only the first plurality of shield wires, and wherein the first plurality of shield wires are coupled to ground;
- a second plurality of shield wires associated with a second plurality of clock lines connected to the clock signal, wherein the second plurality of clock lines is shielded by only the second plurality of shield wires, and wherein the second plurality of shield wires are coupled to Vdd;
- a first plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the first plurality of clock activity program circuits is coupled to one clock line of the first plurality of clock lines and is programmable to select one of an inverted and non-inverted clock signal to be output onto its corresponding clock line;
- and
- a second plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the second plurality of clock activity program circuits is coupled to one clock line of the second plurality of clock lines and is programmable to select one of an inverted and non-inverted clock signal to be output onto its corresponding clock line.
2 more elements
A clock network, comprising:
- a first plurality of shield wires associated with a first plurality of clock lines connected to a clock signal, wherein the first plurality of clock lines is shielded by only the first plurality of shield wires;
- and
- a second plurality of shield wires associated with a second plurality of clock lines connected to the clock signal, wherein the second plurality of clock lines are shielded by only the second plurality of shield wires, and wherein the first plurality of shield wires is coupled to Vdd and the second plurality of shield wires is coupled to ground to evenly reduce current in the clock network during a clock cycle.
Dependencies are inferred from the claim text.