Phase interpolation circuit suitable for wide range frequency input and output characteristics stabilizing method thereof

A data processing device, comprising:

• a transmitting module;
• and
• a receiving module having a clock data recovery circuit, the clock data recovery circuit including:
• a phase interpolation circuit including:
• a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals, wherein the waveform shaping unit includes:
• a current mode logic buffer in which an output resistance value is adaptively changed according to a frequency of the first or second phase offset input clock signal pair, and
• a skewed feedback loop maintaining voltage swing levels of the first and second buffered clock signals at a constant level regardless of the frequency, the skewed feedback loop including:
• a skewed current mode logic buffer configured to receive the first and second buffered clock signals and to generate feedback first and second clock signals that are skew-controlled;
• a converter configured to receive the feedback first and second clock signals and to output a single clock pulse having a duty cycle corresponding thereto;
• and
• a control logic unit configured to adaptively change the output resistance value of the current mode logic (CML) buffer in response to the single clock pulse;
• and
• a phase interpolator configured to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal;
• and
• a clock data recovery main part performing a clock data recovery operation using the phase interpolation output clock signal.

An input unit for a phase interpolator, the input unit comprising:

• a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals to the phase interpolator, the first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals the waveform shaping unit including:
• a current mode logic buffer in which an output resistance value is adaptively changed according to a frequency of the first or second phase offset input clock signal pair, and
• a skewed feedback loop that maintains a voltage swing level of the first and second buffered clock signals at a constant level regardless of frequency, the skewed feedback loop including:
• a skewed current mode logic buffer configured to receive the first and second buffered clock signals and to generate feedback first and second clock signals that are skew-controlled,
• a converter configured to receive the feedback first and second clock signals and to output a single clock pulse having a duty cycle corresponding thereto, and
• a control logic unit configured to adaptively change the output resistance value of the current mode logic buffer in response to the single clock pulse.

A phase interpolation circuit, comprising:

• a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals, wherein the waveform shaping unit includes a current mode logic buffer in which an output resistance value is adaptively changed according to a frequency of the first or second phase offset input clock signal pair, the current mode logic buffer including:
• a first and second input nodes receiving the first or second phase offset input clock signal pair,
• first and second output nodes outputting the first and second buffered clock signals,
• a current source array including a plurality of parallel current sources,
• a first switch block including a plurality of switches, each of switches being connected in series to a corresponding current source in the current source array,
• a resistor array including resistor pairs installed corresponding to the plurality of parallel current sources, and connected to the first and second output nodes,
• a second switch block including switch pairs connected between corresponding resistor pairs of the resistor array and a power supply terminal, respectively;
• and
• an output resistance control unit connected to the current source array, the first and second input nodes, and the first and second output nodes to output the first and second buffered clock signals that are adaptively waveform-shaped according to the frequency of the first or second buffered clock signals pairs;
• and
• a phase interpolator configured to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.