Back to results
US 8,558,595 B2Granted
Semiconductor integrated circuit device
AssigneeKabushiki Kaisha Toshiba
InventorChen Kong Teh
Life of this patent
Estimating the term…
Abstract
In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.
Claims14
A semiconductor integrated circuit device comprising:
- a first charging circuit connected between a first power supply and a first node and configured to charge the first node based on a first signal and a second signal generated by delaying and inverting the first signal;
- a second charging circuit connected between the first power supply and a second node and configured to charge the second node based on the first signal and the second signal;
- a first discharging path connected between the first node and a third node, and including a first switching circuit configured to be turned on and off according to the first signal, and a second switching circuit connected in series to the first switching circuit and configured to be turned on and off according to a fifth signal obtained by an operation of a third signal and a fourth signal;
- a second discharging path connected between the second node and the third node, and including a third switching circuit configured to be turned on and off according to the first signal and a fourth switching circuit connected in series to the third switching circuit and configured to be turned on and off according to a sixth signal generated by inverting the third signal;
- and
- a fifth switching circuit connected between the third node and a second power supply and configured to be turned on and off according to the second signal.
3 more elements
A semiconductor integrated circuit device comprising:
- a first charging circuit connected between a first power supply and a first node, and configured to charge the first node based on a first signal and a third signal obtained by operation of a signal generated by delaying the first signal and a second signal;
- a second charging circuit connected between the first power supply and a second node, and configured to charge the second node based on the first signal and the third signal;
- a first discharging path connected between the first node and a third node, and including a first switching circuit configured to be turned on and off according to the first signal and a second switching circuit connected in series to the first switching circuit and configured to be turned on and off according to a fourth signal;
- a second discharging path connected between the second node and the third node and including a third switching circuit configured to be turned on and off according to the first signal and a fourth switching circuit connected in series to the second switching circuit and configured to be turned on and off according to a fifth signal generated by inverting the fourth signal;
- and
- a fifth switching circuit connected between the third node and a second power supply and configured to be turned on and off according to the third signal.
3 more elements
A semiconductor integrated circuit device comprising:
- a first charging circuit connected between a first power supply and a first node, and configured to charge the first node based on a first signal and a fourth signal obtained by an operation of a signal generated by delaying the first signal, a second signal, and a third signal;
- a second charging circuit connected between the first power supply and a second node, and configured to charge the second node based on the first signal and the fourth signal;
- a first discharging path connected between the first node and a third node and including a first switching circuit configured to be turned on and off according to the first signal and a second switching circuit connected in series to the first switching circuit and configured to be turned on and off according to a fifth signal;
- a second discharging path connected between the second node and the third node and including a third switching circuit configured to be turned on and off according to the first signal and a fourth switching circuit connected in series to the third switching circuit and configured to be turned on and off according to a sixth signal generated by inverting the fifth signal;
- and
- a fifth switching circuit connected between the third node and a second power supply and configured to be turned on and off according to the fourth signal.
3 more elements
Dependencies are inferred from the claim text.