Reduced frequency clock delivery with local recovery

A method comprising:

• generating a clock signal, in an integrated circuit;
• distributing the clock signal, through a clock tree, to a plurality of leaf nodes in each of a plurality of functional units, wherein said distributing includes providing the clock signal to at least one flop circuit in at least one of the plurality of leaf nodes;
• receiving, at the at least one flop circuit, data transmitted at a first frequency and the clock signal transmitted at a second frequency that is one half of the first frequency;
• and
• transmitting, from the at least one flop circuit, a first bit of the data responsive to a first edge of the clock signal and transmitting a second bit of the data responsive to a second edge of the clock signal that is a next edge subsequent to the first edge;
• wherein the method further comprises:
• a first latch of the flop circuit latching the first bit of data responsive to the first edge of the clock signal;
• a second latch of the flop circuit latching the second bit of data responsive to the second edge of the clock signal;
• a multiplexer selecting an output from the first latch responsive to the second edge of the clock signal;
• and
• the multiplexer selecting an output from the second latch responsive to the first edge of the clock signal.

An integrated circuit comprising:

• a clock generator configured to generate a clock signal;
• a clock tree configured to distribute the clock signal;
• and
• a plurality of functional units each having a plurality of leaf nodes, wherein each of the plurality of leaf nodes is coupled to receive the clock signal from the clock tree, wherein at least one of the plurality of leaf nodes includes a plurality of flop circuits coupled to receive the clock signal from the clock tree, wherein each of the flop circuits includes:
• a first latch configured to latch data received on a data input responsive to a first edge of a clock signal;
• a second latch configured to latch data received on the data input responsive to a second edge of the clock signal, wherein a transition of the second edge is opposite of a transition of the first edge;
• and
• a multiplexer configured to output data received from the first latch responsive to the second edge of the clock signal and further configured to output data received from the second latch responsive to the first edge of the clock signal.