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US 8,558,593 B2Granted
Frequency-doubling delay locked loop
AssigneeMosaid Technologies Incorporated
InventorPaul W. Demone
Life of this patent
Estimating the term…
Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
Claims15
An integrated circuit comprising:
- a delay line including a plurality of delay stages,
- the delay line configured to receive a reference clock signal, and
- the plurality of delay stages configured to provide respective delay stage output signals;
- a detector circuit in communication with the delay line and configured to detect a first edge, a second edge, a third edge, and a fourth edge of respective first, second, third, and fourth ones of the delay stage output signals;
- and
- a flip-flop in communication with the detector circuit, configured to provide an output signal, and further configured to:
- set the output signal when the detector circuit detects the first edge;
- reset the output signal when the detector circuit detects the second edge;
- set the output signal when the detector circuit detects the third edge;
- and
- reset the output signal when the detector circuit detects the fourth edge.
8 more elements
An integrated circuit comprising:
- a delay line including a plurality of delay stages,
- the delay line configured to receive a reference clock signal, and
- the plurality of delay stages configured to provide respective delay stage output signals;
- a detector circuit in communication with the delay line and configured to detect:
- a first edge and a second edge of a first one of the delay stage output signals provided by the plurality of delay stages, and
- a first edge and a second edge of a second one of the delay stage output signals provided by the plurality of delay stages;
- and
- a flip-flop in communication with the detector circuit, configured to provide an output signal, and further configured to:
- set the output signal when the detector circuit detects the first edge of the first one of the delay stage output signals,
- reset the output signal when the detector circuit detects the first edge of the second one of the delay stage output signals,
- set the output signal when the detector circuit detects the second edge of the first one of the delay stage output signals, and
- reset the output signal when the detector circuit detects the second edge of the second one of the delay stage output signals.
9 more elements
Dependencies are inferred from the claim text.