Fully digital method for generating sub clock division and clock waves
AssigneeDialog Semiconductor GmbH
InventorsNir Dahan, Kevin Graham Allen
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Abstract
The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.
Claims22
A digital circuit for generating sub clock division and clock waves comprising:
- a combined positive and negative clock gate,
- a clock output generated by said combined positive and negative clock gate,
- a clock input coupled to a counter circuit and to said combined positive and negative clock gate,
- a positive comparator,
- a negative comparator,
- an output from said counter circuit coupled to said positive comparator and to said negative comparator,
- an enable positive clock signal in said combined positive and negative clock gate generated from an output from said positive comparator, and
- an enable negative clock signal in said combined positive and negative clock gate generated from an output from said negative comparator.
A method of providing a digital circuit for generating sub clock division and clock waves comprising the steps of:
- providing a combined positive and negative clock gate,
- generating a clock output by said combined positive and negative clock gate,
- providing a clock input coupled to a counter circuit and to said combined positive and negative clock gate,
- providing a positive comparator,
- providing a negative comparator,
- providing an output from said counter circuit coupled to said positive comparator and to said negative comparator,
- providing an enable positive clock signal in said combined positive and negative clock gate generated from an output from said positive comparator, and
- providing an enable negative clock signal in said combined positive and negative clock gate generated from an output from said negative comparator.
Dependencies are inferred from the claim text.