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US 8,558,588 B2Granted
Clock divider circuit and system LSI having same
AssigneeFujitsu Semiconductor Limited
InventorTakayuki Kume
Life of this patent
Estimating the term…
Abstract
A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register within the preset register group, and imparts the dividing ratios stored in the selected preset register to the plurality of dividers.
Claims9
A clock divider circuit, comprising:
- a plurality of dividers each having a dividing ratio setting register in which a dividing ratio is settable, and each dividing an input clock according to the dividing ratio set in the dividing ratio setting register;
- a preset register group having a plurality of preset registers each of which stores the dividing ratios being set for the dividing ratio setting registers of the plurality of dividers;
- and
- a selector that selects a single preset register within the preset register group, and provides the dividing ratios stored in the selected preset register to the dividing ratio setting registers of the plurality of dividers, wherein
- each of the dividing ratio setting registers is configured to be able to be set with a dividing ratio supplied from an external circuit.
2 more elements
A clock divider circuit, comprising:
- a plurality of dividers for which dividing ratios are settable;
- a plurality of preset registers each storing dividing ratios being set for the plurality of dividers;
- a selector that selects any of the plurality of preset registers, and outputs the dividing ratios stored in the selected preset register to the plurality of dividers;
- and
- a control circuit configured to, in response to a first request signal, which requests selection of a preset register, have the selector select the preset register being selected by the first request signal among the plurality of preset registers so as to set the dividing ratios stored in the selected preset register to the plurality of dividers and in response to a second request signal that requests setting a dividing ratio to an individual divider among the plurality of dividers, set a dividing ratio supplied with the second request signal to a divider specified by the second request signal.
2 more elements
A system LSI, comprising:
- a CPU;
- a plurality of internal circuits;
- and
- a clock divider circuit that divides an input clock and outputs the divided clock to the CPU and the plurality of internal circuits, wherein
- the clock divider circuit comprises:
- a plurality of dividers, for which dividing ratios are settable, that divide the input clock corresponding to the dividing ratios and respectively output the divided clock to the plurality of internal circuits,
- a plurality of preset registers each storing dividing ratios being set in the plurality of dividers,
- a selector that selects any of the plurality of preset registers, and outputs the dividing ratios stored in the selected preset register to the plurality of dividers,
- and
- a control circuit configured to, in response to a first request signal, which is supplied from the CPU and requests selection of a preset register, have the selector select the preset register being selected by the first request signal among the plurality of preset registers so as to set the dividing ratios stored in the selected preset register to the plurality of dividers, and in response to a second request signal that is supplied from the CPU and requests setting a dividing ratio to an individual divider among the plurality of dividers, set a dividing ratio supplied with the second request signal to a divider specified by the second request signal.
7 more elements
Dependencies are inferred from the claim text.