Low latency inter-die trigger serial interface for ADC

A method comprising:

• in response to an asserting of a trigger signal on a first die, supplying a multi-bit value to a first serial bus interface, wherein the first serial bus interface is part of the first die;
• communicating the multi-bit value from the first serial bus interface to a second serial bus interface of a second die, wherein the first serial bus interface supplies a serial bus clock signal to the second serial bus interface, and wherein the multi-bit value includes a sample/hold value;
• in response to receiving the sample/hold value onto the second die, asserting a sample/hold signal to a plurality of sample/hold circuits of the second die, wherein a latency period between a time when the trigger signal is asserted on the first die and a time when the sample/hold signal is asserted on the second die is less than eight periods of the serial bus clock signal;
• performing an analog-to-digital conversion in an analog-to-digital converter (ADC) on the first die such that the ADC outputs an ADC output value;
• and
• storing the ADC output value in a data buffer of the first die, wherein the first die and the second die are parts of a packaged controller.

An assembly comprising:

• an analog-to-digital converter (ADC) disposed on a first die;
• a plurality of sample/hold circuits disposed on a second die;
• an analog multiplexer disposed on the second die and controllable to couple a selected one of the sample/hold circuits to the ADC;
• and
• means for receiving a trigger signal and in response thereto communicating a multi-bit value in serial fashion from the first die to the second die, wherein the means supplies a serial bus clock signal from the first die to the second die, wherein the means is also for:
• 1) causing a sample/hold signal supplied to the plurality of sample hold circuits to be asserted, and 2) controlling the analog multiplexer such that the selected one of the sample/hold circuits is coupled to the ADC, and such that a latency period between a time when the trigger signal is received and a time when the sample/hold signal is asserted is less than eight periods of the serial bus clock signal, and wherein the means is also for causing the ADC to perform an analog-to-digital conversion thereby outputting an ADC output value.