Data channel circuit with reference clock signal free of glitches

A data channel circuit comprising:

• an analog to digital converter configured to, based on a first clock signal, convert an analog signal into a digital signal;
• a control circuit configured to (i) receive the digital signal from the analog to digital converter, and (ii) generate a second clock signal based on the digital signal, wherein the second clock signal has pulses, wherein each of the pulses has a predetermined duration;
• an interpolator circuit configured to (i) receive the second clock signal, and (ii) generate a reference clock signal based on the second clock signal, wherein the second clock signal has glitches, wherein each of the glitches has a duration shorter than the predetermined duration;
• and
• a deglitch circuit configured to (i) receive the reference clock signal, and (ii) based on the reference clock signal, generate the first clock signal, wherein the first clock signal does not include the glitches,
• wherein the deglitch circuit comprises
• a locked loop and is configured to (i) establish a first duty cycle based on the reference clock signal, and (ii) provide feedback for the locked loop based on the first duty cycle,
• a first plurality of transistors configured to, based on the reference clock signal, generate the first clock signal, and
• a first capacitance configured to charge based on current received from an output of the first plurality of transistors,
• wherein the first plurality of transistors are configured to generate the first clock signal based on a charged state of the first capacitance.

A data channel circuit comprising:

• an analog to digital converter configured to, based on a first clock signal, convert an analog signal into a digital signal;
• a control circuit configured to (i) receive the digital signal from the analog to digital converter, and (ii) generate a second clock signal based on the digital signal;
• an interpolator circuit configured to
• receive the second clock signal, and
• generate a reference clock signal based on a selected one of (i) the second clock signal or (ii) the second clock signal delayed by a predetermined amount of phase delay;
• and
• a first circuit comprising
• a first pair of transistors configured to generate a third clock signal based on the reference clock signal,
• a first inverter configured generate a fourth clock signal based on the third clock signal, and
• a first transistor configured to (i) receive an output of one of the first plurality of transistors, and (ii) adjust current through the first plurality of transistors based on the fourth clock signal, and
• a second circuit comprising
• a second pair of transistors configured to (i) receive the fourth clock signal, and (ii) generate a fifth clock signal based on the fourth clock signal, and
• a second inverter configured generate the first clock signal based on the fifth clock signal.