Digital glitch filter
AssigneeFreescale Semiconductor, Inc.
InventorJinglin Zhang
Life of this patent
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Abstract
A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.
Claims19
A digital glitch filter for filtering an input signal, comprising:
- a first flip-flop for generating a first intermediate signal based on detection of a negative glitch in the input signal, wherein the input signal is provided to at least one of a set terminal and a reset terminal of the first flip-flop;
- a second flip-flop for generating a second intermediate signal based on detection of a positive glitch in the input signal, wherein an inverted input signal is provided to at least one of a set terminal and a reset terminal of the second flip-flop;
- and
- a synchronizer, connected to the first and second flip-flops, for generating a filtered output signal based on the first and second intermediate signals, wherein the synchronizer includes,
- a first logic gate connected to at least one of an output terminal and an inverted output terminal of the first flip-flop;
- a second logic gate connected to at least one of an output terminal and an inverted output terminal of the second flip-flop and an output terminal of the first logic gate;
- a third flip-flop, having an input terminal connected to an output terminal of the second logic gate and an output terminal connected to an input terminal of the first logic gate, for generating a third intermediate signal based on the first and second intermediate signals;
- and
- a fourth flip-flop, having a data input terminal connected to the output terminal of the third flip-flop, for generating the filtered output signal based on the third intermediate signal.
A digital glitch filter for filtering an input signal, comprising:
- a first latch for generating a first intermediate signal based on detection of a negative glitch in the input signal, wherein the input signal is provided to at least one of a set terminal and a reset terminal of the first latch;
- a second latch for generating a second intermediate signal based on detection of a positive glitch in the input signal, wherein an inverted input signal is provided to at least one of a set terminal and a reset terminal of the second latch;
- a synchronizer, connected to the first and second latches, for generating a filtered output signal based on the first and second intermediate signals, wherein the synchronizer includes,
- an AND gate connected to an inverted output terminal of the first latch;
- an OR gate connected to an output terminal of the second latch and an output terminal of the AND gate;
- a first flip-flop, having a data input terminal connected to an output terminal of the OR gate and an output terminal connected to an input terminal of the AND gate, for generating a third intermediate signal based on the first and second intermediate signals;
- and
- a second flip-flop, having a data input terminal connected to the output terminal of the first flip-flop, for generating the filtered output signal based on the third intermediate signal.
Dependencies are inferred from the claim text.