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US 8,558,576 B2Granted
Output buffer
AssigneeKabushiki Kaisha Toshiba
InventorYuui Shimizu
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.
Claims14
An output buffer comprising:
- a clamp output stage comprising a first clamp output part and a second clamp output part, wherein at least one of the first clamp output part and second clamp output part is configured to clamp a drain potential of a P-channel field effect transistor or a drain potential of an N-channel field effect transistor to an intermediate potential between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor by inserting a field effect transistor for potential clamp in series between the P-channel field effect transistor and the N-channel field effect transistor and inputting an intermediate level between the high potential and the low potential into a gate of the field effect transistor for potential clamp;
- an output equalizing circuit configured to average an output level of the first clamp output part and an output level of the second clamp output part per cycle;
- and
- a data input part configured to be connected to the front of the clamp output stage and to input a data signal into a gate of the P-channel field effect transistor and a gate of the N-channel field effect transistor based on an enable signal during data output, wherein the data input part comprises:
- a NAND circuit configured to output NAND by the data signal and the enable signal to the gate of the P-channel field effect transistor;
- and
- a NOR circuit configured to output NOR by the data signal and an enable inversion signal which is inverted from the enable signal to the gate of the N-channel field effect transistor.
4 more elements
An output buffer comprising:
- a first clamp output part in which a first field effect transistor for potential clamp is inserted in series between a first P-channel field effect transistor and a first N-channel field effect transistor, an intermediate level between a high potential supplied to a source of the first P-channel field effect transistor and a low potential supplied to a source of the first N-channel field effect transistor is input into a gate of the first field effect transistor for potential clamp and a data signal is input into a gate of the first P-channel field effect transistor and a gate of the first N-channel field effect transistor;
- and
- a second clamp output part in which a second field effect transistor for potential clamp is inserted in series between a second P-channel field effect transistor and a second N-channel field effect transistor, an intermediate level between a high potential supplied to a source of the second P-channel field effect transistor and a low potential supplied to a source of the second N-channel field effect transistor is input into a gate of the second field effect transistor for potential clamp, and a data inversion signal which is inverted from the data signal is input into a gate of the second P-channel field effect transistor and a gate of the second N-channel field effect transistor.
An output buffer comprising:
- a first clamp output part configured to clamp a drain potential of a first P-channel field effect transistor or a drain potential of a first N-channel field effect transistor by inserting a first field effect transistor for potential clamp in series between the first P-channel field effect transistor and the first N-channel field effect transistor and inputting an intermediate level between a high potential supplied to a source of the first P-channel field effect transistor and a low potential supplied to a source of the first N-channel field effect transistor into a gate of the first field effect transistor for potential clamp;
- a second clamp output part configured to clamp a drain potential of a second P-channel field effect transistor or a drain potential of a second N-channel field effect transistor by inserting a second field effect transistor for potential clamp in series between the second P-channel field effect transistor and the second N-channel field effect transistor and inputting an intermediate level between a high potential supplied to a source of the second P-channel field effect transistor and a low potential supplied to a source of the second N-channel field effect transistor into a gate of the second field effect transistor for potential clamp;
- a first data input part configured to be connected to the front of the first clamp output part and to input a data signal into a gate of the first P-channel field effect transistor and a gate of the first N-channel field effect transistor based on an enable signal;
- and
- a second data input part configured to be connected to the front of the second clamp output part and to input a data inversion signal which is inverted from the data signal into a gate of the second P-channel field effect transistor and a gate of the second N-channel field effect transistor based on the enable signal.
2 more elements
Dependencies are inferred from the claim text.