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US 8,558,320 B2Granted
Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior
AssigneeQUALCOMM Incorporated
InventorsHaining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
Life of this patent
Estimating the term…
Abstract
An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
Claims23
An integrated circuit device comprising:
- a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, each disposed on a surface of a semiconductor substrate, the second semiconductor structure between the first and the third semiconductor structures, and arranged proximately to each of the first and third semiconductor structures, a first space defined between the first and the second semiconductor structures, and a second space defined between the second and the third semiconductor structures;
- a first and second plurality of conductive structures, each disposed on the surface of the semiconductor substrate, the first and second plurality of conductive structures distributed in the first and second spaces, respectively, at least a first one of the first plurality of conductive structures placed closer to the first semiconductor structure than to the second semiconductor structure, and at least a second one of the first plurality of conductive structures placed closer to the second semiconductor structure than to the first semiconductor structure, wherein a first group of the first plurality of conductive structures has a first offset from a line of symmetry between the first and second semiconductor structures, and a second group of the first plurality of conductive structures has a second offset from the line of symmetry, the first and second offsets substantially canceling out, the second plurality of conductive structures having an asymmetric pattern that mirrors a pattern of the first plurality of conductive structures.
An integrated circuit device comprising:
- a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, each disposed on a surface of a semiconductor substrate, the second semiconductor structure between the first and the third semiconductor structures, and arranged proximately to each of the first and third semiconductor structures, a first space defined between the first and the second semiconductor structures, and a second space defined between the second and the third semiconductor structures;
- and
- first and second means for conducting electric charge, each of the first and second conducting means being disposed on the surface of the semiconductor substrate, the first and second conducting means arranged within the first and second spaces, respectively, the first conducting means having respective non-zero offsets from a line of symmetry between the first and second semiconductor structures, the respective non-zero offsets having asymmetrical Resistive Capacitive (RC) effects that add substantially to zero, the second conducting means having an asymmetric pattern that mirrors a pattern of the first conducting means.
A method for fabricating an integrated circuit, the method comprising:
- forming first, second and third semiconductor structures on a semiconductor substrate, the second semiconductor structure between the first and the third semiconductor structures, and arranged proximately to each of the first and third semiconductor structures, a first space defined between the first and the second semiconductor structures, and a second space defined between the second and the third semiconductor structures;
- and
- forming a first and second plurality of conductive structures within the first and second spaces, respectively, the first plurality of conductive structures arranged asymmetrically and with offsetting Resistive Capacitive (RC) behavior, the second plurality of conductive structures having an asymmetric arrangement that mirrors the arrangement of the first plurality of conductive structures.
A method for fabricating an integrated circuit, the method comprising the steps of:
- forming first, second and third semiconductor structures on a semiconductor substrate, the second semiconductor structure between the first and the third semiconductor structures, and arranged proximately to each of the first and third semiconductor structures, a first space defined between the first and the second semiconductor structures, and a second space defined between the second and the third semiconductor structures;
- and
- forming a first and second plurality of conductive structures within the first and second spaces, respectively, the first plurality of conductive structures arranged asymmetrically and with offsetting Resistive Capacitive (RC) behavior, the second plurality of conductive structures having an asymmetric arrangement that mirrors the arrangement of the first plurality of conductive structures.
Dependencies are inferred from the claim text.