US 8,558,318 B2Granted

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

AssigneeTexas Instruments Incorporated

InventorsAngelo Pinto, Frank S Johnson, Benjamin P McKee, Shaofeng Yu

Life of this patent

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Abstract

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Claims6

Dependent claims

An integrated circuit, comprising:

a substrate, comprised of silicon having a first crystal lattice orientation;
a layer of directly bonded silicon (DSB) having a second crystal lattice orientation formed on a top surface of said substrate;
regions of STI field oxide formed in said layer of DSB such that the field oxide extends into said substrate;
a layer of selective epitaxial growth (SEG) silicon having said first crystal lattice orientation on said top surface of said substrate in a first region for a first type of MOS transistor;
a first type of well formed in said SEG layer and said substrate in said first region;
an second type of well formed in a second region for a second type of MOS transistor in said DSB layer and said substrate that is different than said first region;
a first type of MOS transistor formed on and in said first type of well;
a second type of MOS transistor formed on and in said second type of well;
a PMD liner formed on top surfaces of said first type of MOS transistor, said second type of MOS transistor and said field oxide region;
a PMD layer formed on a top surface of said PMD liner;
and
contacts formed in said PMD layer and said PMD liner to make electrical connections to said first type of MOS transistor and said second type of MOS transistor.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/007,098Filed 14 Jan 2011 · division
Priority: 24 Dec 2007
Published: US 2011/0108893 A112 May 2011
Granted: 15 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/751
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions
H10D 30/798
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being provided in or under the channel regions

Family

Application61/016,543Us provisional application · filed 24 Dec 2007
Application12/343,794Parent of this division · filed 24 Dec 2008
US 2011/0108893 A1Pre-grant publication · published 12 May 2011
US 7,892,908 B2Parent of this division
US 2009/0159933 A1Published application
US 8,558,318 B2This patent

From the US filing history. Foreign family members aren’t listed.