Semiconductor device and production method

#The present application relates generally to a semiconductor device and method of producing the same.

#Semiconductor devices, particularly integrated circuits using MOS transistors have increasingly been highly integrated. MOS transistors in integrated circuits have been downsized to nano sizes as the integration level is increased. The basic circuit of digital circuits is an inverter circuit. As MOS transistors constituting an inverter circuit are downsized, problems occur such as difficulty in leaking current control, reduced reliability due to hot carrier effect, and difficulty in reducing the area occupied by circuits while assuring the necessary current quantity. In order to resolve these problems, surrounding gate transistors (SGT) have been proposed in which the source, gate, and drain are provided on a substrate in the vertical direction and the gate surrounds an island-shaped semiconductor, and CMOS inverter circuits using SGTs have been proposed (for example, see S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGTs) for Ultra High Density DRAMs,” IEEE JSSC, Vol. 30, No. 9, 1995).

#An inverter is constructed using a pMOS transistor and an nMOS transistor. The mobility of holes is half the mobility of electrons. Therefore, the pMOS transistor must have a gate width double the gate width of the nMOS transistor in an inverter circuit. For this reason, a conventional CMOS inverter circuit using SGTs comprises two pMOS SGTs and one nMOS SGT. In other words, a conventional CMOS inverter circuit using SGTs comprises three island-shaped semiconductors.

#A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

#FIG. 1A is a plane view of primary elements of a semiconductor device according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view at the line X-X′ in FIG. 1A, and FIG. 1C is a cross-sectional view at the line Y-Y′ in FIG. 1A;

#FIG. 2A is a plane view showing one example of a production process of a semiconductor device according to a first embodiment the present invention, FIG. 2B is a cross-sectional view at the line X-X′ in FIG. 2A, and FIG. 2C is a cross-sectional view at the line Y-Y′ in FIG. 2A;

#FIG. 1A is a plane view of an inverter consisting of an nMOS transistor and a pMOS transistor according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view at the line X-X′ in FIG. 1A, and FIG. 1C is a cross-sectional view at the line Y-Y′ in FIG. 1A.

#The inverter according to the first embodiment is described below with reference to FIGS. 1A to 1C. The inverter according to the first embodiment has a pMOS SGT 148 and an nMOS transistor 149. The nMOS transistor 149 is formed so as to surround the pMOS SGT 148.

#The pMOS SGT 148 includes an island-shaped silicon layer 105. A first gate insulating film 124A is formed so as to surround the periphery of the island-shaped silicon layer 105. The first gate insulating film 124A is a high-K film, for example a silicon oxide film, a silicon nitride film, hafnium oxide, hafnium oxynitride, lanthanum oxide or the like. In addition, a gate electrode 125 is formed so as to surround the periphery of the first gate insulating film 124 A. The gate electrode 125 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten or the like. In addition, a first p+ type silicon layer 121 is formed on the top of the island-shaped silicon layer 105 and a second p+ type silicon layer 120 is formed on the bottom of the island-shaped silicon layer 105. In this embodiment, the first p+ type silicon layer 121 serves as the source scattering layer and the second p+ type silicon layer 120 serves as a drain scattering layer. In addition, the island-shaped silicon layer 105 serves as a channel area. In the present embodiment, a channel is formed in the island-shaped silicon layer 105 by a voltage being impressed on the gate electrode 125 during operation.