US 8,558,310 B2 · Indium, carbon and halogen doping for PMOS transistors

Abstract

A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Claims9

Dependent claims

An integrated circuit (IC), comprising:

a substrate having a semiconductor surface;
at least one PMOS transistor formed in said substrate, comprising:
a gate structure including a gate electrode on a gate dielectric formed over said semiconductor surface;
source/drain regions formed in said semiconductor surface on both sides of said gate structure, and
source/drain extension regions formed on both sides of said gate structure including co-doping comprising indium, carbon and a halogen each having minimum peak concentrations of 1×1016/cm3, wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions;
and
wherein said at least one PMOS transistor includes at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said indium, said halogen and said carbon are in said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not in said source/drain extension regions of said non-core PMOS transistor.

4 more elements

A method of forming an integrated circuit (IC) including at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said core PMOS transistor has a gate dielectric that is at least 2 Å of equivalent oxide thickness (EOT) thinner as compared to said non-core PMOS transistor, comprising:

performing PLDD implantation comprising co-implanting indium, carbon and a halogen and a boron comprising specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode comprising polysilicon on a gate dielectric formed on said semiconductor surface, wherein during said PLDD implantation said indium, said halogen and said carbon are implanted into said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not implanted into said source/drain extension regions of said non-core PMOS transistor;
performing source and drain implantation to establish source/drain regions, wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions, and
source/drain annealing after said performing source and drain implantation.

Dependencies are inferred from the claim text.

Indium, carbon and halogen doping for PMOS transistors

Life of this patent

Indium, carbon and halogen doping for PMOS transistors

Life of this patent

Abstract

Claims9