US 8,558,307 B2Granted

Semiconductor device with diffused MOS transistor and manufacturing method of the same

AssigneesSanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC

InventorsShuichi Kikuchi, Kiyofumi Nakaya, Shuji Tanaka

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Abstract

It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.

Claims5

Dependent claims

A semiconductor device comprising:

a semiconductor layer of a first general conductivity type;
a well layer of a second general conductivity type formed in the semiconductor layer;
a diffused metal oxide semiconductor transistor formed in the well layer, the diffused transistor comprising a body layer of the second general conductivity type formed in the well layer, a source layer of the first general conductivity type formed in the body layer, a drain layer of the first general conductivity type formed in the well layer outside the body layer, a gate electrode disposed on the well layer between the source layer and the drain layer so that a part of the body layer operates as a channel region, a first diffusion layer of the first general conductivity type formed in the well layer so as to extend from under the gate electrode toward the drain layer, a second diffusion layer of the first general conductivity type having an impurity concentration higher than the first diffusion layer and formed in the well layer so that a lateral edge of the second diffusion layer on the source layer side is located between a lateral edge of the first diffusion layer on the source layer side and a lateral edge of the drain layer on the source layer side, and an additional diffusion layer of the second general conductivity type formed in the drain layer so as to penetrate into the well layer, a lateral edge of the additional diffusion layer on the source layer side being located in the drain layer so as to be laterally separated from the gate electrode, each of the lateral edges defining a sidewall of a corresponding layer, the second diffusion layer being deeper than the first diffusion layer, and the additional diffusion layer being deeper than the second diffusion layer;
another transistor formed in the semiconductor layer outside the well layer;
an isolation layer formed in the semiconductor layer so as to surround the diffused transistor and the another transistor so that the diffused transistor and the another transistor are disposed in a surrounded region of the semiconductor layer that is surrounded and electrically isolated from other portions of the semiconductor layer by the isolation layer and so that the diffused transistor is not isolated from the another transistor by an isolation layer in the surrounded region;
and a shallow additional diffusion layer of the second general conductivity type formed in the additional diffusion layer so as to have an impurity concentration higher than the additional diffusion layer and to be shallower than the additional diffusion layer.

3 more elements

A method of manufacturing a semiconductor device comprising a diffused metal oxide semiconductor transistor, comprising:

providing a semiconductor layer of a first general conductivity type;
forming a well layer of a second general conductivity type in the semiconductor layer;
forming a first diffusion layer of the first general conductivity type in the well layer;
forming a gate electrode on the well layer so as to cover an edge portion of the first diffusion layer;
forming a body layer of the second general conductivity type in the well layer so that a part of the body layer is located under the gate electrode;
forming a source layer in the body layer adjacent the gate electrode;
forming a drain layer in the well layer outside the body layer;
forming a second diffusion layer of the first general conductivity type having an impurity concentration higher than the first diffusion layer in the well layer so that a lateral edge of the second diffusion layer on the source layer side is located between a lateral edge of the first diffusion layer on the source layer side and a lateral edge of the drain layer on the source layer side, each of the lateral edges defining a sidewall of a corresponding layer;
forming an additional diffusion layer of the second general conductivity type in the drain layer so as to penetrate into the well layer, a lateral edge of the additional diffusion layer on the source layer side being located in the drain layer so as to be laterally separated from the gate electrode;
forming a shallow additional diffusion layer of the second general conductivity type in the additional diffusion layer so as to have an impurity concentration higher than the additional diffusion layer and to be shallower than the additional diffusion layer;
forming a transistor in the semiconductor layer outside the well layer;
and forming an isolation layer in the semiconductor layer so as to surround a region of the semiconductor layer, wherein the well layer and the transistor are disposed in the surrounded region of the semiconductor layer surrounded by the isolation layer, and the diffused transistor is not isolated from the transistor by an isolation layer in the surrounded region, and the second diffusion layer is deeper than the first diffusion layer, and the additional diffusion layer is deeper than the second diffusion layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/958,531Filed 18 Dec 2007
Published: US 2009/0152628 A118 Jun 2009
Granted: 15 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 62/307
Having lateral doping variations: the doping variations being parallel to the channel lengths
H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions