Semiconductor device and method of manufacturing the same

A semiconductor device, comprising:

• a device isolation layer defining a plurality of active regions formed in a semiconductor substrate;
• an interlayer insulating film formed over the device isolation layer;
• a first bit line region that divides the interlayer insulating film into two parts, wherein a width of a lower portion of the first bit line is narrower than that of an upper portion of the first bit line;
• a storage node contact hole exposing two neighboring active regions;
• a storage node contact plug material provided in the storage node contact hole;
• a second bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall;
• a first spacer formed over a sidewall of the first bit line region;
• a second spacer formed over a sidewall and a bottom of the second bit line region;
• and
• a first bit line and a second bit line formed in the first and the second bit line regions, respectively.

A semiconductor device comprising:

• a first bit line pattern including a first bit line conductive pattern and a first bit line mask pattern formed over the first bit line conductive pattern;
• a second bit line pattern including a second bit line conductive pattern and a second bit line mask pattern formed over the second bit line conductive pattern;
• first and second device isolation layers arranged at an angle with respect to the first bit line pattern so that the first bit line pattern passes between a first interlayer insulating film of the first device isolation layer and a second interlayer insulating film of the second device isolation layer;
• first and second active regions arranged at an angle with respect to the second bit line pattern so that the second bit line pattern passes between a first storage node contact plug of the first active region and a second storage node contact plug of the second active region;
• a first spacer formed between the second bit line conductive pattern;
• and any of the first and the second storage node contact plugs;
• and
• a second spacer extending from the first spacer and formed between the second bit line mask pattern and any of the first and the second storage node contact plugs,
• wherein the first spacer is thicker than the second spacer.