Method for manufacturing a power device being integrated on a semiconductor substrate, in particular having a field plate vertical structure and corresponding device

A semiconductor device, comprising:

• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the gate region;
• the semiconductor device further comprising:
• a trench having first region and a second region that is wider than the first region, the first and second regions having respective first and second sidewalls, at least the second sidewall being adjacent to the drain, body, and first source regions;
• wherein the gate insulator is disposed over respective first portions of the first and second sidewalls;
• and
• wherein the source insulator is disposed over respective second portions of the first and second sidewalls that are under the respective first portions of the first and second sidewalls.

A semiconductor device, comprising:

• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the gate region;
• the semiconductor device further comprising:
• a trench having first region and a second region that is wider than the first region, the first and second regions having respective first and second sidewalls, at least the second sidewall being adjacent to the drain, body, and first source regions;
• wherein the gate insulator is disposed over respective first portions of the first and second sidewalls;
• wherein the source insulator is disposed over respective second portions of the first and second sidewalls that are under the respective first portions of the first and second sidewalls;
• and
• wherein the second source region is disposed adjacent to the source insulator only in the second region of the trench.

A semiconductor device, comprising:

• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the gate region;
• the semiconductor device further comprising:
• a trench having first region and a second region that is wider than the first region, the first and second regions having respective first and second sidewalls, at least the second sidewall being adjacent to the drain, body, and first source regions, the second sidewall having a portion that forms an approximately right angle with the first sidewall;
• wherein the gate insulator is disposed over respective first portions of the first and second sidewalls;
• and
• wherein the source insulator is disposed over respective second portions of the first and second sidewalls that are under the respective first portions of the first and second sidewalls.

A semiconductor device, comprising:

• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the gate region;
• the semiconductor device further comprising:
• a trench having first region and a second region that is wider than the first region, the first and second regions having respective first and second sidewalls, at least the second sidewall being adjacent to the drain, body, and first source regions, the second sidewall having a portion that forms an acute angle with the first sidewall;
• wherein the gate insulator is disposed over respective first portions of the first and second sidewalls;
• and
• wherein the source insulator is disposed over respective second portions of the first and second sidewalls that are under the respective first portions of the first and second sidewalls.

A semiconductor device, comprising:

• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the gate region;
• the semiconductor device further comprising:
• a trench having first region and a second region that is wider than the first region, the first and second regions having respective first and second sidewalls, at least the second sidewall being adjacent to the drain, body, and first source regions, the second sidewall having a portion that forms an obtuse angle with the first sidewall;
• wherein the gate insulator is disposed over respective first portions of the first and second sidewalls;
• and
• wherein the source insulator is disposed over respective second portions of the first and second sidewalls that are under the respective first portions of the first and second sidewalls.

A system, comprising:

• a first integrated circuit, comprising:
• a drain region;
• a body region disposed over the drain region;
• a first source region disposed over the body region;
• a gate insulator disposed adjacent to the body region;
• a gate region disposed adjacent to the gate insulator and having an edge that delimits a vertical perimeter;
• a source insulator disposed adjacent to the drain region;
• and
• a second source region disposed adjacent to the source insulator and laterally offset from the vertical edge of the gate region;
• and
• a second integrated circuit coupled to the first integrated circuit.