Semiconductor memory devices and methods of manufacturing and operating same
AssigneesSamsung Electronics Co., Ltd., Seoul National University Industry Foundation
InventorsSeunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Abstract
A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.
Claims19
A semiconductor device comprising:
- a non-hydrophobic layer;
- a channel layer on the non-hydrophobic layer, the channel layer including a plurality of first nanostructures;
- a hydrophobic layer on the non-hydrophobic layer around the channel layer;
- a source electrode and a drain electrode on the hydrophobic layer and contacting both ends of the channel layer, respectively;
- a first tunnel insulation layer on the channel layer, the first tunnel insulation layer including sequentially stacked first and second insulation layers, and the second insulation layer is one of a hydrophilic molecular layer and a hydrophobic molecular layer;
- a first charge trap layer on the first tunnel insulation layer, the first charge trap layer including a plurality of second nanostructures different from the plurality of first nanostructures;
- a first blocking insulation layer on the first charge trap layer;
- and
- a first control gate on the first blocking insulation layer.
A method of manufacturing a semiconductor device, the method comprising:
- providing a non-hydrophobic layer;
- forming a hydrophobic layer on the non-hydrophobic layer, the hydrophobic layer having an opening that exposes a first area of the non-hydrophobic layer;
- forming a channel layer on the first area exposed by the opening, the channel layer including a plurality of first nanostructures, the channel layer being formed on the nonhydrophobic layer and the hydrophobic layer being on the non-hydrophobic layer around the channel layer;
- forming a source electrode and a drain electrode contacting both ends of the channel layer and on the hydrophobic layer;
- forming a first tunnel insulation layer on the channel layer including,
- sequentially stacking first and second insulation layers, the second insulation layer being one of a hydrophilic molecular layer and a hydrophobic molecular layer;
- forming a first charge trap layer on the first tunnel insulation layer, the first charge trap layer including a plurality of second nanostructures different from the plurality of first nanostructures;
- forming a first blocking insulation layer on the first charge trap layer;
- and
- forming a first control gate on the first blocking insulation layer.
A semiconductor device comprising:
- a non-hydrophobic layer;
- a channel layer on the non-hydrophobic layer, the channel layer including a plurality of first nanostructures;
- a hydrophobic layer on the non-hydrophobic layer around the channel layer;
- a source electrode and a drain electrode on the hydrophobic layer and contacting both ends of the channel layer, respectively;
- a first tunnel insulation layer on the channel layer;
- a first charge trap layer on the first tunnel insulation layer, the first charge trap layer including a plurality of second nanostructures different from the plurality of first nanostructures;
- a first blocking insulation layer on the first charge trap layer;
- a first control gate on the first blocking insulation layer;
- a second control gate spaced apart from the channel layer, the channel layer between the first and second control gates;
- a second charge trap layer between the channel layer and the second control gate;
- a second tunnel insulation layer between the channel layer and the second charge trap layer;
- and
- a second blocking insulation layer between the second charge trap layer and the second control gate.
Dependencies are inferred from the claim text.