Semiconductor element and solid-state imaging device

A solid-state imaging device comprising a plurality of pixels being arrayed, each of the pixels comprising:

• a base-body region implemented by a semiconductor of a first conductivity type;
• a charge-generation buried region of a second conductivity type, being buried in a part of an upper portion of the base-body region so as to implement a photodiode together with the base-body region, configured to create a first potential valley in the base-body region;
• an accumulation region of the second conductivity type, being buried in a part of the upper portion of the base-body region, separately from the charge-generation buried region, configured to create a second potential valley deeper than the first potential valley, where direction of field toward which signal charges generated by the photodiode move is defined as depth direction;
• a transfer-gate insulation film provided on a surface of the base-body region between the charge-generation buried region and the accumulation region;
• a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region;
• and
• a recessed-potential creation means configured to create a stair-like-shaped potential barrier for electronic shuttering, the stair-like-shaped potential barrier has a shoulder level at a side of the second potential valley, the shoulder level is lower by one stage in a potential barrier reduction direction than top level of the first potential valley, between the first potential valley and the second potential valley;
• a read-out region of the second conductivity time, being buried in a part of the upper portion of the base-body region, separately from the accumulation region, configured to receive signal charges transferred from the accumulation region, and to store the transferred signal charges until at a time of reading out;
• a read-out gate insulation film provided on a surface of the base-body region between the accumulation region and the read-out region;
• and
• a read-out-gate electrode provided on the read-out gate insulation film, configured to control a potential of a read-out channel formed in the base-body region between the accumulation region and the read-out region,
• wherein, by applying simultaneously a voltage to the transfer-gate electrodes in each of pixels, keeping a qualitative level relation between the top level and the shoulder level, a height of the top level of electronic-shuttering potential barrier is changed by voltages applied to the transfer-gate electrode in each of pixels so that a height of the shoulder level is lower than a bottom of the second potential valley when the signal charges are transferred respectively from the charge-generation buried region to the accumulation region in each of pixels so as to execute global electronic shuttering, and so that the height of the shoulder level becomes higher than the bottom of the second potential valley just before the signal charges are transferred from the accumulation region to the read-out region.