Semiconductor device with dual metal silicide regions and methods of making same

A device, comprising:

• an NMOS transistor with a gate electrode structure positioned above a semiconducting substrate and a PMOS transistor with a gate electrode structure positioned above said semiconducting substrate;
• a plurality of N-doped source/drain regions formed in said substrate proximate said gate electrode structure of said NMOS transistor;
• a plurality of P-doped source/drain regions formed in said substrate proximate said gate electrode structure of said PMOS transistor;
• a first metal silicide region formed in each of said source/drain regions for said NMOS transistor and said PMOS transistor, said first metal silicide region having an inner boundary;
• and
• a tensile-stressed second metal silicide region formed in each of said N-doped source/drain regions for said NMOS transistor and having a substantially same thickness as said first metal silicide regions, said second metal silicide region being positioned laterally between said inner boundary of said first metal silicide region in said N-doped source/drain regions and an edge of said gate electrode structure of said NMOS transistor, wherein said second metal silicide regions create a tensile stress in a channel region of said NMOS transistor.

A method, comprising:

• forming a gate electrode structure for an NMOS transistor above a semiconducting substrate;
• forming a plurality of N-doped source/drain regions in said substrate proximate said gate electrode structure;
• performing a first silicidation process to form a first metal silicide region in each of said N-doped source/drain regions, said first metal silicide region having an inner boundary;
• and
• after forming said first metal silicide regions, performing a second silicidation process to form a tensile-stressed second metal silicide region in each of said N-doped source/drain regions so as to have a substantially same thickness as said first metal silicide regions, said second metal silicide region being positioned laterally between said inner boundary of said first metal silicide region and an edge of said gate electrode structure, wherein said second metal silicide regions create a tensile stress in a channel region of said NMOS transistor.

A method, comprising:

• forming a gate electrode structure for an NMOS transistor above a semiconducting substrate;
• forming a gate electrode structure for a PMOS transistor above a semiconducting substrate;
• forming a plurality of N-doped source/drain regions in said substrate proximate said gate electrode structure of said NMOS transistor;
• forming a plurality of P-doped source/drain regions in said substrate proximate said gate electrode structure of said PMOS transistor;
• performing a first silicidation process to form a first metal silicide region in each of said N-doped source/drain regions and in each of said P-doped source/drain regions, said first metal silicide region having an inner boundary;
• and
• after forming said first metal silicide regions, performing a second silicidation process to form a second metal silicide region in each of said N-doped source/drain regions, said second metal silicide region being positioned laterally between said inner boundary of said first metal silicide region and an edge of said gate electrode structure of said NMOS transistor, wherein said first and second metal silicide regions are formed in said N-doped source/drain regions so as to have a substantially same thickness.