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AssigneeHRL Laboratories, LLC
InventorsDean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
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A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising:
Dependencies are inferred from the claim text.
Gate electrodes for field-effect devices: for FETs
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
Being Group III-V materials, e.g. GaAs: nitride Group III-V materials, e.g. AlN or GaN
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates
About 5 years 1 month of term left · ends 2 Dec 2031 (estimated)
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This disclosure relates to gate formation for field effect transistors, and in particular to formation of gates with high aspect ratios.
Next-generation gallium nitride (GaN) high electron mobility transistors (HEMTs) require aggressive scaling of device dimensions to reduce device delays, access resistances, and parasitic capacitances for improved high-frequency performance. In particular, ultra-short nanometer-scale gate length and source-drain spacing are required. Also needed is a robust, high throughput, reproducible, and reliable process for such small geometries. Conventionally, high-frequency GaN HEMTs are fabricated using e-beam lithography, metal evaporation and lift-off for T-shaped gate formation. However, using the conventional fabrication processes, the aspect ratio h/Lg defined by the ratio of height (h) 11 of the gate and length 13 of the gate foot (Lg), as shown in height of FIG. 1B, is limited, which decreases the gate head-to-channel distance, giving rise to parasitic capacitances. Furthermore, device uniformity, yield, and minimum gate length relies on alignment accuracy and resolution of e-beam lithography tools, limiting minimum dimensions of scaled devices.
FIGS. 1A and 1B show the limitations of the conventional processes for fabrication in accordance with the prior art;
FIG. 2 shows a flow diagram of a self-aligned sidewall gate fabrication process in accordance with the present disclosure; and
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present disclosure.
In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention.
Conventionally, the fabrication process for GaN HEMTs uses e-beam lithography for gate foot/head definition followed by metal evaporation and lift-off. To achieve high performance, a high aspect ratio of the gate height to gate foot length (h/Lg) is required, and high aspect ratios greater than 5 are desirable. However, the use of conventional evaporation and sputter metallization fabrication techniques for high aspect ratio gates may result in evaporation of gate metal 10 from the gate sidewalls 12, as shown by evaporated region 14, shown in FIG. 1A. FIG. 1A shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and low process yield.
FIG. 1B shows a similar issue which may occur during metal sputtering. Metal deposition at the top opening 17 grows faster than at the bottom of the opening 18, which may result in an air-void 16 in the gate structure, which increases gate resistance, limits device performance, limits uniformity and reduces process yield.