Passivation layer for packaged chip
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Puu Jeng, Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu, Tzuan-Horng Liu, Tzu-Wei Chiu, Kuo-Ching Hsu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Puu Jeng, Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu, Tzuan-Horng Liu, Tzu-Wei Chiu, Kuo-Ching Hsu
Estimating the term…
The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
A packaged integrated circuit (IC) chip, comprising:
A packaged integrated circuit (IC) chip, comprising:
A method of forming a packaged integrated circuit (IC) chip, comprising:
Dependencies are inferred from the claim text.