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US 8,558,208 B2Granted
Resistance random access memory including variable-resistance layers
AssigneeKabushiki Kaisha Toshiba
InventorsRyota Fujitsuka, Masahiro Kiyotoshi, Katsuyuki Sekine, Mitsuru Sato
Life of this patent
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Abstract
According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other.
Claims10
A resistance random access memory comprising:
- a first electrode;
- a second electrode;
- a first variable-resistance layer and a second variable-resistance layer that are arranged between the first electrode and the second electrode;
- and
- at least one non variable-resistance layer that is arranged so that positions of the first variable-resistance layer and the second variable-resistance layer between the first electrode and the second electrode are symmetrical to each other, wherein
- the first variable-resistance layer is arranged to be in contact with the first electrode,
- the second variable-resistance layer is arranged to be in contact with the second electrode, and
- the at least one non variable-resistance layer is arranged between the first variable-resistance layer and the second variable-resistance layer to be in contact with the first variable-resistance layer and the second variable-resistance layer, and wherein
- the at least one non variable-resistance layer includes
- a first non variable-resistance layer arranged to be in contact with the first variable-resistance layer, and
- a second non variable-resistance layer arranged to be in contact with the second variable-resistance layer, and
- a third electrode is arranged between the first non variable-resistance layer and the second non variable-resistance layer.
9 more elements
A resistance random access memory, comprising:
- a first electrode;
- a second electrode;
- a first variable-resistance layer and a second variable-resistance layer that are arranged between the first electrode and the second electrode;
- and
- at least one non variable-resistance layer that is arranged so that positions of the first variable-resistance layer and the second variable-resistance layer between the first electrode and the second electrode are symmetrical to each other,
- wherein the at least one non variable-resistance layer includes
- a first non variable-resistance layer arranged between the first variable-resistance layer and the first electrode, and
- a second non variable-resistance layer arranged between the second variable-resistance layer and the second electrode, and
- a third electrode is arranged between the first variable-resistance layer and the second variable-resistance layer.
6 more elements
A resistance random access memory, comprising:
- a first electrode;
- a second electrode;
- a first variable-resistance layer and a second variable-resistance layer that are arranged between the first electrode and the second electrode;
- and
- at least one non variable-resistance layer that is arranged so that positions of the first variable-resistance layer and the second variable-resistance layer between the first electrode and the second electrode are symmetrical to each other,
- wherein the first and second variable-resistance layers are a transition metal oxide layer or a layer containing transition metal oxide, and
- the at least one non variable-resistance layer is a layer containing an insulator.
4 more elements
Dependencies are inferred from the claim text.