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US 8,557,681 B2Granted
III-nitride wafer fabrication
AssigneeInternational Rectifier Corporation
InventorsThomas Herman, Robert Beach
Life of this patent
Estimating the term…
Abstract
A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.
Claims19
A method of fabricating a semiconductor wafer, comprising:
- forming stress reduction trenches in a surface of a silicon substrate, said stress reduction trenches residing in regions designated to serve as dicing streets, said stress reduction trenches greater than one hundred times wider than deep, said dicing streets wider than said stress reduction trenches;
- growing a III-nitride body over said surface of said silicon substrate, said III-nitride body filling said stress reduction trenches, wherein said III-nitride body extends continuously over a boundary between said surface and at least one of said stress reduction trenches, and wherein a stress relief crack is formed in said III-nitride body over at least one of said stress reduction trenches;
- and
- dicing said semiconductor wafer into individual devices by cutting said semiconductor wafer along said dicing streets.
1 more element
A method of fabricating a semiconductor wafer, comprising:
- forming stress reduction trenches in a surface of a silicon substrate, said stress reduction trenches residing in regions designated to serve as dicing streets, said stress reduction trenches greater than one hundred times wider than deep, said dicing streets wider than said stress reduction trenches;
- growing a III-nitride body over said surface of said silicon substrate, wherein said III-nitride body extends continuously over a boundary between said surface and at least one of said stress reduction trenches;
- filling said stress reduction trenches with said III-nitride body to form stress relief cracks in said III-nitride body over said stress reduction trenches;
- and
- dicing said semiconductor wafer into individual devices by cutting said semiconductor wafer along said dicing streets.
2 more elements
A method of fabricating a semiconductor wafer, comprising:
- forming stress reduction trenches in a surface of a silicon substrate, said stress reduction trenches residing in regions designated to serve as dicing streets, said stress reduction trenches greater than one hundred times wider than deep, said dicing streets wider than said stress reduction trenches;
- growing a III-nitride body over said surface of said silicon substrate, said III-nitride body filling said stress reduction trenches, wherein said III-nitride body extends continuously over a boundary between said surface and at least one of said stress reduction trenches, and wherein a stress relief crack is formed in said III-nitride body over at least one of said stress reduction trenches;
- forming a plurality of III-nitride devices over said III-nitride body;
- and
- dicing said semiconductor wafer into individual III-nitride devices by cutting said semiconductor wafer along said dicing streets.
2 more elements
Dependencies are inferred from the claim text.