Methods for fabricating integrated circuits

A method for fabricating an integrated circuit comprising:

• etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins;
• epitaxially growing a layer of undoped silicon to form an upper, undoped region of the fins;
• forming dummy gate structures overlying and transverse to the plurality of fins;
• filling between the dummy gate structures with a back fill material;
• removing the dummy gate structures to expose a portion of the fins;
• depositing a high-k dielectric material and a work function determining gate electrode material overlying the portion of the fins;
• removing the back fill material to expose a second portion of the fins;
• forming metal silicide contacts on the second portion of the fins;
• and
• forming conductive contacts to the work function determining material and to the metal silicide, wherein forming dummy gate structures comprises:
• forming a layer of insulator overlying the fins;
• depositing a layer of silicon germanium overlying the layer of insulator;
• depositing a layer of hard mask material overlying the layer of silicon germanium;
• patterning the layer of hard mask material, layer of silicon germanium, and layer of insulator to form dummy gate stacks;
• and
• forming sidewall spacers on the dummy gate stacks.

A method for fabricating an integrated circuit comprising:

• etching trenches into a semiconductor substrate to define sidewalls of spaced apart semiconductor fins having top surfaces;
• filling the trenches with an insulating material such that the insulating material is planar with the top surfaces of the fins;
• forming dummy gate structures overlying the insulating material and first regions of the fins, wherein second regions of the fins are defined between the dummy gate structures;
• covering the second regions of the fins with a fill material;
• removing the dummy gate structures to expose the top surfaces of the first regions of the fins;
• etching the insulating material to expose the sidewalls of the first regions of the fins;
• forming a gate structure overlying the top surfaces and sidewalls of the first regions of the fins;
• removing the fill material to expose the top surfaces of the fins in the second regions;
• forming contacts on the top surfaces of the second regions of the fins;
• wherein forming dummy gate structures comprises:
• forming a layer of insulator overlying the fins and the insulating material;
• depositing a layer of silicon germanium overlying the layer of insulator;
• depositing a layer of hard mask material overlying the layer of silicon germanium;
• patterning the layer of hard mask material, layer of silicon germanium, and layer of insulator to form dummy gate stacks;
• and
• forming sidewall spacers on the dummy gate stacks.