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US 8,557,665 B2Granted
Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
AssigneeInternational Business Machines Corporation
InventorsGuy M. Cohen, Paul M. Solomon
Life of this patent
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Abstract
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
Claims20
A method of forming a double-gate FET comprising:
- forming a structure including a single-crystal semiconductor film with a gate dielectric on its top and bottom surfaces, a bottom-gate, and a top-gate with dielectric sidewall spacers;
- implanting ions into said single-crystal semiconductor film forming a source region and a drain region in said single-crystal semiconductor film and on opposing sides of the top-gate;
- forming sacrificial spacers adjacent a sidewall of said top-gate and directly on a portion of said single-crystal semiconductor film;
- defining sub-lithographic source and drain regions by etching unmasked regions of said single-crystal semiconductor film, a portion of said source region, and a portion of said drain region not protected by said sacrificial spacers and said top-gate, wherein a single-crystal semiconductor film portion is provided beneath the sacrificial spacers and said top-gate and has sidewall edges that are vertical coincident to sidewall edges of said sacrificial spacers;
- providing a first planarized dielectric on said structure;
- recessing said first planarized dielectric below an upper surface of said top-gate;
- removing said sacrificial spacers to expose top surfaces of said sub-lithographic defined source and drain regions;
- forming a metal-semiconductor alloy on said exposed surfaces of said source and drain regions utilizing a metal film, wherein a portion of said metal film which does not form a metal-semiconductor alloy is located atop the first planarized dielectric;
- depositing a second planarized dielectric over at least said metal-semiconductor alloy;
- and
- etching selectively said metal over said dielectric sidewall spacers.
8 more elements
A method of forming a double-gate FET comprising:
- forming a structure including a single-crystal semiconductor film with a gate dielectric on its top and bottom surfaces, a bottom-gate, and a top-gate with dielectric sidewall spacers;
- implanting ions into said single-crystal semiconductor film forming a source region and a drain region in said single-crystal semiconductor film and on opposing sides of the top-gate
- forming sacrificial spacers adjacent a sidewall of said top-gate and directly on a portion of said single-crystal semiconductor film;
- defining sub-lithographic source and drain regions by etching unmasked regions of said single-crystal semiconductor film, a portion of said source region, and a portion of said drain region not protected by said sacrificial spacers and said top-gate, wherein a single-crystal semiconductor film portion is provided beneath the sacrificial spacers and said top-gate and has sidewall edges that are vertical coincident to sidewall edges of said sacrificial spacers;
- providing a first planarized dielectric on said structure;
- recessing said first planarized dielectric below an upper surface of said top-gate;
- removing said sacrificial spacers to expose top surfaces of said sub-lithographic defined source and drain regions;
- and
- forming a metal-semiconductor alloy on said exposed surfaces of said source and drain regions utilizing a metal film, wherein a portion of said metal film which does not form a metal-semiconductor alloy is located atop the first planarized dielectric.
6 more elements
Dependencies are inferred from the claim text.