Method for manufacturing semiconductor device with vertical gate transistor
AssigneeHynix Semiconductor Inc.
InventorHeung-Jae Cho
Life of this patent
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Abstract
A method for manufacturing a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a gate dielectric layer on sidewalls of the pillars and on surfaces of the semiconductor substrate between the pillars, forming an implant damage in a portion of the gate dielectric layer between two pillars by implanting ions into the portion of the gate dielectric layer, forming vertical gates to cover the sidewalls of the pillars, and removing the implant damage.
Claims18
A method for manufacturing a semiconductor device, comprising:
- forming a plurality of pillars by etching a semiconductor substrate;
- forming a gate dielectric layer on sidewalls of the plurality of pillars and on surfaces of the semiconductor substrate between the plurality of pillars, thereby forming first portions of the gate dielectric layer and second portions of the gate dielectric layer, respectively;
- forming implant damages in the second portions of the gate dielectric layer by implanting ions into the second portions of the gate dielectric layer;
- forming vertical gates to cover the sidewalls of the plurality of pillars;
- and
- removing the implant damages.
A method for manufacturing a semiconductor device, comprising:
- forming a plurality of pillars by etching a semiconductor substrate;
- forming a gate dielectric layer on sidewalls of the plurality of pillars and on surfaces of the semiconductor substrate between the plurality of pillars, thereby forming first portions of the gate dielectric layer and second portions of the gate dielectric layer, respectively;
- forming a conductive layer that gap-fills trenches between the plurality of pillars, wherein an upper surface of the conductive layer is formed to a height lower than those of upper surfaces of the plurality of pillars;
- forming a spacer dielectric layer on an entire surface including the conductive layer and the plurality of pillars;
- forming an implant damages in the second portions of the gate dielectric layer by implanting ions into the second portions of the gate dielectric layer;
- forming vertical gates by sequentially performing etching of the spacer dielectric layer and etching of the conductive layer;
- and
- removing the implant damages.
A method for manufacturing a semiconductor device, comprising:
- forming a plurality of pillars by etching a semiconductor substrate;
- forming a gate dielectric layer on sidewalls of the plurality of pillars and on surfaces of the semiconductor substrate between the plurality of pillars, thereby forming first portions of the gate dielectric layer and second portions of the gate dielectric layer, respectively;
- removing the second portions of the gate dielectric layer;
- forming a conductive layer that gap-fills trenches between the plurality of pillars, wherein an upper surface of the conductive layer is formed to a height lower than those of upper surfaces of the plurality of pillars;
- forming a spacer dielectric layer on an entire surface including the conductive layer and the plurality of pillars;
- and
- forming vertical gates by sequentially performing etching of the spacer dielectric layer and etching of the conductive layer.
Dependencies are inferred from the claim text.