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US 8,557,658 B2Granted
Multi-transistor non-volatile memory element
AssigneeTaiwan Semiconductor Manufacting Company, Ltd.
InventorsShih Wei Wang, Chun Juang Lin
Life of this patent
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Abstract
The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.
Claims9
A method of forming a first and second multi-transistor element comprising:
- providing a substrate having a first active region and a second active region disposed in the substrate;
- forming a shallow trench isolation feature in the substrate;
- forming a floating gate stack adjacent to the isolation feature, the floating gate stack including a first region associated with the first multi-transistor element, a second region associated with the second multi-transistor element, and a notch interposing the first and second regions;
- forming a control gate stack adjacent to the floating gate stack;
- forming a common source region associated with the first and second multi-transistor elements, wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region;
- forming a first bitline coupled to the first region of the floating gate stack;
- forming a second bitline coupled to the second region of the floating gate stack;
- using the first bitline as a read bitline and the second bitline as a program bitline;
- and
- forming a wordline adjacent to the floating gate stack and the control gate stack.
7 more elements
A method of forming a device, comprising:
- providing a substrate having a first active region, a second active region, and a third region;
- forming a floating gate stack adjacent to the third region, the floating gate stack including a first portion associated with a first multi-transistor element, a second portion associated with a second multi-transistor element, and a notch interposing the first and second portions;
- forming a control gate stack adjacent to the floating gate stack;
- forming a common source region associated with the first and second multi-transistor elements;
- forming a first bitline coupled to the first region of the floating gate stack;
- and
- forming a second bitline coupled to the second region of the floating gate stack;
- wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region,
- wherein the third region is an isolation region,
- wherein the third region includes a shallow trench isolation.
7 more elements
A method of forming a first and second multi-transistor element, comprising:
- providing a substrate having a first active region and a second active region disposed in the substrate;
- forming an isolation feature in the substrate;
- forming a floating gate stack proximate to the isolation feature, the floating gate stack including a first region associated with the first multi-transistor element, a second region associated with the second multi-transistor element, and a notch interposing the first and second regions;
- forming a control gate stack adjacent to the floating gate stack;
- implanting a common source region associated with the first and second multi-transistor elements, wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region;
- forming a first signal line adjacent to the floating gate stack and the control gate stack;
- implanting first and second drains adjacent the signal line;
- forming a second signal line coupled to the first region of the floating gate stack;
- forming a third signal line coupled to the second region of the floating gate stack;
- and
- using the second signal line as a read bitline and the third signal line as a program bitline;
- wherein the first signal line is a wordline.
9 more elements
Dependencies are inferred from the claim text.