Transistor device with reduced gate resistance

A method for forming a device with reduced gate resistance, comprising:

• forming a conductive sheet in a first dielectric material;
• depositing a second dielectric material on the first dielectric material and the conductive sheet;
• forming one or more openings in the second dielectric material down to the conductive sheet;
• forming one or more conductive fingers in the one more openings in contact with the conductive sheet to form an embedded gate structure;
• depositing a gate dielectric layer on the one or more conductive fingers;
• forming a channel layer on the gate dielectric layer;
• and
• forming source and drain electrodes at end portions of a channel region of the channel layer.