US 8,557,636 B1Granted

Stacked semiconductor substrates

AssigneeAltera Corporation

InventorRakesh H. Patel

Life of this patent

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Abstract

A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA.

Claims19

Dependent claims

A method for forming a semiconductor system in a package comprising the steps of:

modifying a pre-existing circuit design for a semiconductor integrated circuit to add a plurality of through-silicon-vias along at least one peripheral edge of the circuit,
fabricating a first integrated circuit in a first semiconductor substrate in accordance with the modified design, said first semiconductor substrate having first and second major surfaces with circuits defined in the first major surface and through-silicon-vias extending through a peripheral region of the first semiconductor substrate between the first and second major surfaces of the first semiconductor substrate,
forming a redistribution layer on the second major surface of the first semiconductor substrate that is connected to the through-silicon-vias in the peripheral region of the first semiconductor substrate,
mounting the first semiconductor substrate on a package substrate with the first major surface of the first semiconductor substrate facing the package substrate, and
mounting a second integrated circuit in a second semiconductor substrate on the first semiconductor substrate and in mechanical and electrical connection therewith wherein circuits in the second integrated circuit are connected to circuits in the first integrated circuit through the redistribution layer and the through-silicon-vias.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/613,992Filed 13 Sep 2012 · division
Priority: 31 Aug 2006
Granted: 15 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 90/00
Package configurations
H10W 72/01
Interconnections or connectors in packages: manufacture or treatment
H10W 72/07252
Characterised by changes in properties of the bump connectors during connecting: changes in structures or sizes

Family

Application60/842,116Us provisional application · filed 31 Aug 2006
Application11/897,916Parent of this continuation-in-part · filed 31 Aug 2007
Application11/969,373Parent of this continuation-in-part · filed 4 Jan 2008
Application12/431,625Parent of this division · filed 28 Apr 2009
US 8,294,252 B1Parent of this division
US 8,000,106 B1Parent of this continuation-in-part
Application12/431,625Parent of this continuation-in-part
US 8,557,636 B1This patent

From the US filing history. Foreign family members aren’t listed.