Stacked semiconductor device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsShoko Omizo, Atsushi Yoshimura, Fumihiro Iwami
Life of this patent
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Abstract
In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
Claims16
A method of manufacturing a stacked semiconductor device, comprising:
- preparing a first semiconductor wafer including plural first chip areas sectioned by first dicing grooves and each having first electrode pads formed at a circuit surface, and first photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural first chip areas to expose the first electrode pads;
- and
- stacking a second semiconductor wafer including plural second chip areas sectioned by second dicing grooves and each having second electrode pads formed at a circuit surface, and second photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural second chip areas to expose the second electrode pads, with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers while facing a non-circuit surface of the first semiconductor wafer and the circuit surface of the second semiconductor wafer to form plural chip stacked bodies of the first chip areas and the second chip areas,
- wherein the first chip area and the second chip area are stacked in a staircase pattern to expose the second electrode pads.
A method of manufacturing a stacked semiconductor device, comprising:
- preparing a first semiconductor wafer including plural first chip areas sectioned by first dicing grooves and each having first electrode pads formed at a circuit surface, and first photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural first chip areas to expose the first electrode pads;
- holding a second semiconductor wafer including plural second chip areas divided by second dicing grooves in half-cut states and each having second electrode pads formed at a circuit surface, and second photosensitive surface protection and adhesive layers provided at each of the circuit surfaces of the plural second chip areas to expose the second electrode pads, with a supporting substrate attached to the circuit surface of the second semiconductor wafer via the second photosensitive surface protection and adhesive layers;
- sectioning the plural second chip areas by grinding a non-circuit surface of the second semiconductor wafer held by the supporting substrate;
- and
- stacking the second semiconductor wafer on the first semiconductor wafer via the first photosensitive surface protection and adhesive layers while facing the circuit surface of the first semiconductor wafer and the non-circuit surface of the second semiconductor wafer to form plural chip stacked bodies of the first chip areas and the second chip areas,
- wherein the first chip area and the second chip area are stacked in a staircase pattern to expose the first electrode pads.
Dependencies are inferred from the claim text.