Method for fabrication of a semiconductor device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist
Life of this patent
Estimating the term…
Abstract
A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
Claims30
A method to process an Integrated Circuit device comprising:
- processing a first layer of first transistors, then
- processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then
- processing a second metal layer overlaying said first metal layer, then
- processing a second layer of second transistors overlaying said second metal layer, wherein
- said second metal layer is connected to provide power to at least one of said second transistors.
A method to process an Integrated Circuit device comprising:
- processing a first layer of first transistors, then
- processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then
- processing a second metal layer overlaying said first metal layer, then
- processing a second layer of second transistors overlaying said second metal layer, then processing a third metal layer overlying said second transistors, wherein at least one of said second transistors is provided with a back-bias.
A method to process an Integrated Circuit device comprising:
- processing a first layer of first transistors, then
- processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then
- processing a second metal layer overlaying said first metal layer, then
- processing a second layer of second transistors overlaying said second metal layer, comprising
- forming at least one connection path between said second transistors and said second metal layer, wherein
- said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.
A method to process an Integrated Circuit device comprising:
- processing a first layer of first transistors, then
- processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then
- processing a second metal layer overlaying said first metal layer, then
- processing a second layer of second transistors overlaying said second metal layer, then
- processing a third metal layer overlying said second transistors,
- wherein at least one of said second transistors is one of:
- (i) a replacement-gate transistor;
- (ii) a Finfet transistor;
- or
- (iii) a double gate horizontally oriented transistor.
Dependencies are inferred from the claim text.