Method, a mechanism and a computer program product for executing several tasks in a multithreaded processor

A multithreaded (MT) processor comprising an at least partially hardware based mechanism for executing several tasks, each task having, for every hardware shared resource from a predetermined set of hardware shared resources in the MT processor, one associated artificial time delay that is introduced when said task accesses said hardware shared resource,

• wherein the at least partially hardware based mechanism includes
• means for establishing, for every hardware shared resource in the predetermined set of hardware shared resources and each task to be artificially time delayed, the artificial time delay to be applied to each access of said task to said hardware shared resource;
• means for verifying if a request is ready to be sent to said shared resource;
• hardware based computing means for verifying if the shared resource is ready to accept said request;
• means for delaying said request by the artificial delay established for said shared resource;
• and
• hardware based computing means for allowing the request of the task to access said shared resource.

A mechanism for executing several HRT tasks simultaneously in a multithreaded (MT) processor, the mechanism comprising

• means for establishing a set of parameters relating to the configuration of the MT processor;
• means for determining, according to the established set of parameters, the maximum delay, for every resource of a predetermined set of resources shared by at least two of the HRT tasks in the MT processor, that each of said HRT tasks can suffer when accessing said shared resource;
• the mechanism for executing several tasks in a MT processor executing each HRT task in isolation, wherein the established artificial delay for the task is the maximum delay and each HRT task is delayed when accessing every shared resource according to said artificial delay;
• means for computing the Worst Case Execution Time (WCET) for each HRT task, which takes into account the MT processor configuration set of parameters;
• means for verifying if the computed WCET for each HRT task fits a given suitable scheduling of the HRT tasks;
• means for configuring the MT processor in a mode in which no artificial delay is introduced to the HRT tasks when said tasks access shared resources;
• and,
• means for executing the HRT tasks according to said mode.

A multithreaded (MT) processor comprising a processor architecture including hardware structures and software, the architecture configured for the MT processor to execute several tasks, each task having, for every hardware shared resource from a predetermined set of hardware shared resources in the MT processor, one associated artificial time delay that is introduced when said task accesses said hardware shared resource,

• the processor architecture including:
• one or both of an at least partially hardware based structure and software configured to establish, for every hardware shared resource in the predetermined set of hardware shared resources and each task to be artificially time delayed, the artificial time delay to be applied to each access of said task to said hardware shared resource;
• one or both of an at least partially hardware based structure and software configured to verify if a request is ready to be sent to said shared resource;
• one or both of an at least partially hardware based structure and software configured to verify if the shared resource is ready to accept said request;
• one or both of an at least partially hardware based structure and software configured to delay said request by the artificial delay established for said shared resource;
• and
• one or both of an at least partially hardware based structure and software configured to allow the request of the task to access said shared resource.