Direct hardware processing of internal data structure fields
AssigneeQLOGIC, Corporation
InventorsGovind Kizhepat, Kenneth Y. Y. Choy, Suresh Kadiyala
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AssigneeQLOGIC, Corporation
InventorsGovind Kizhepat, Kenneth Y. Y. Choy, Suresh Kadiyala
Estimating the term…
In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.
A data processing method comprising employing at least one processor to perform the steps of:
A non-transitory computer-readable medium encoding instructions to perform a method comprising the steps of:
A data processing apparatus having a processor comprising:
Dependencies are inferred from the claim text.