US 8,555,234 B2 · Verification of soft error resilience

Abstract

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.

Claims20

Dependent claims

A method for verification of soft error resilience of devices from design data for a logic design, comprising:

selecting a statistically relevant set of Soft Error Rate (SER) sensitive logic devices deemed critical to a SER robustness for a test process of the logic design by using a SER categorization tool to generate a SER sensitive device test set, and further comprising:
successively filtering the design data through a series of heuristic rule-based device identifiers that group and annotate the SER sensitive logic devices by parsing a netlist representing the logic design for identification nomenclature, device type and connectivity;
selecting, grouping, and associating related devices for testing according to a list of predetermined SER sensitive device types;
and
reducing a number of the devices in the SER sensitive device test set based on symmetry of structures joined to a common bus and further reducing flow device vectors to scalars;
and
inducing a logic state fault in successive ones of said reduced number of devices in said test process of the logic design for functional design verification which provides a sufficient delay after injection for the logic design to detect a logic fault for those reduced number of devices in said test process;
and
providing logic fault information of said detected logic fault of said reduced number of devices to facilitate corrective action.

6 more elements

A computer program product stored on a memory device of a computer processing system as a tangible embodiment of information comprising instructions for execution by the computer processing system to perform a method for automated verification of soft error resilience of devices from design data for a logic design, the method comprising:

selecting a statistically relevant set of Soft Error Rate (SER) sensitive logic devices deemed critical to a SER robustness for a test process of the logic design by using a SER categorization tool to generate a SER sensitive device test set, and further comprising:
successively filtering the design data through a series of heuristic rule-based device identifiers that group and annotate the SER sensitive logic devices by parsing a netlist representing the logic design for identification nomenclature, device type and connectivity;
selecting, grouping, and associating related devices for testing according to a list of predetermined SER sensitive device types;
and
reducing a number of the devices in the SER sensitive device test set based on symmetry of structures joined to a common bus and further reducing flow device vectors to scalars;
inducing a logic state fault in successive ones of said reduced number of devices in said test process of the logic design for functional design verification which provides a sufficient delay after injection for the logic design to detect a logic fault for those reduced number of devices in said test process;
and
providing logic fault information of said detected logic fault of said reduced number of devices to facilitate corrective action.

5 more elements

A system for verification of soft error resilience of devices from design data for a logic design, comprising:

a computer processing system having memory and processing facilities for processing data with a computer program for analysis of failure rates of devices from said design data;
a fault injection and exercising environment for inducing faults in devices from said design data;
and
said computer program for analysis of failure rates of devices from said design data being stored in said memory of said computer processing system and upon execution of said computer program and exercise of said fault injection and exercising environment for said design data, said computer program provides a Soft Error Rate (SER) rate value for devices of said design data for verification of soft error resilience of the devices from said design data, and further provides selection of a statistically relevant set of SER sensitive logic devices from the design data for the analysis, the statistically relevant set of SER sensitive logic devices formed by successively filtering the design data through a series of heuristic rule-based device identifiers that group and annotate the SER sensitive logic devices by parsing a netlist representing the logic design for identification nomenclature, device type and connectivity, and selects, groups and associates related devices for testing according to a list of predetermined SER sensitive device types, and reduces a number of the devices in the SER sensitive device test set based on symmetry of structures joined to a common bus and further reduces flow device vectors to scalars.

1 more element

Dependencies are inferred from the claim text.

Verification of soft error resilience

Life of this patent

Verification of soft error resilience

Life of this patent

Abstract

Claims20