Integrated circuit optimization modeling technology

A data processing system adapted for performing a design optimization method for reducing leakage power for a target circuit design specified by a machine-readable file, comprising:

• a processor and memory storing a computer-implemented model of timing constrained, leakage power reduction achievable by applying gate length modifications to cells in a circuit design as a function of a set of characteristics of circuit designs including respective pluralities of circuit paths, values of said set of characteristics for the target circuit design, and instructions executable by the processor;
• the instructions including logic to apply the computer-implemented model using said values to produce an indication of susceptibility of the target design to optimization by a procedure to modify said target circuit design using said timing constrained, gate length modifications, and logic to determine whether to execute the procedure to implement gate length modification in the target circuit design in response to the indication.

An article of manufacture comprising:

• a non-transitory, machine readable storage medium storing a computer-implemented model of timing constrained, leakage power reduction achievable by applying gate length modifications to cells in a circuit design as a function of a set of characteristics of circuit designs including respective pluralities of circuit paths, values of said set of characters for a target circuit design, and instructions executable by a processor;
• the instructions including logic to apply the computer-implemented model using said values to produce an indication of susceptibility of the target design to optimization by a procedure to modify said target circuit design using said timing constrained, gate length modifications, and logic to determine whether to execute the procedure to implement gate length modification in the target circuit design in response to the indication.